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ADP3418 Datasheet(PDF) 5 Page - ON Semiconductor |
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ADP3418 Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 13 page ADP3418 Rev. 6 | Page 5 of 13 | www.onsemi.com PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DRVH 8 SW 7 PGND 6 DRVL 5 BST 1 IN 2 3 VCC 4 AD3418 TOP VIEW (Not to Scale) OD Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 BST Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be between 100 nF and 1 µF. 2 IN Logic Level Input. This pin has primary control of the drive outputs. 3 OD Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low. 4 VCC Input Supply. This pin should be bypassed to PGND with a ~1 µF ceramic capacitor. 5 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET. 6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET. 7 SW This pin is connected to the buck switching node, close to the upper MOSFET’s source. It is the floating return for the upper MOSFET drive signal. 8 DRVH Buck Drive. Output drive for the upper (buck) MOSFET. |
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