REV. B

ADP3415

–9–

Shutdown

For optimal system power management, when the output voltage

is not needed, the ADP3415 can be shut down to conserve power.

When the SD pin is high, the ADP3415 is enabled for normal

operation. Pulling the SD pin low forces the DRVH and DRVL

outputs low, turning the buck converter OFF and reducing the

VCC supply current to less than 40 µA.

Undervoltage Lockout

The undervoltage lockout (UVLO) circuit holds both FET

driver outputs low during VCC supply ramp-up. The UVLO

logic becomes active and in control of the driver outputs at a

supply voltage of no greater than 1.5 V. The UVLO circuit

waits until the VCC supply has reached a voltage high enough

to bias logic level FETs fully ON, around 4.1 V, before releas-

ing control of the drivers to the control pins.

Thermal Shutdown

The thermal shutdown circuit protects the ADP3415 against

damage due to excessive power dissipation. Under extreme

conditions, high ambient temperature and high power dissipa-

tion, the die temperature may rise up to the thermal shutdown

threshold of 165°C. If the die temperature exceeds 165°C, the

thermal shutdown circuit will turn the output drivers OFF. The

drivers remain disabled until the junction temperature has

decreased by 10°C, at which point the drivers are again enabled.

APPLICATION INFORMATION

Supply Capacitor Selection

For the supply input (VCC) of the ADP3415, a local bypass

capacitor is recommended to reduce the noise and to supply

some of the peak currents drawn. Use a 10 µF MLC capacitor.

Keep the ceramic capacitor as close as possible to the ADP3415.

Multilayer ceramic (MLC) capacitors provide the best combina-

tion of low ESR and small size and can be obtained from the

following vendors:

Murata

GRM235Y5V106Z16

www.murata.com

Taiyo-Yuden

EMK325F106ZF

www.t-yuden.com

Tokin

C23Y5V1C106ZP

www.tokin.com

Bootstrap Circuit

and a Schottky diode, D1, as shown in Figure 2. Selecting these

components can be done after the high-side FET has been chosen.

The bootstrap capacitor must have a voltage rating that is able

to handle the maximum battery voltage plus 5 V. The capaci-

tance is determined using the following equation

C

Q

V

BST

GATE

BST

=

∆

(1)

and

drive. For example, the IRFR8503 has a total gate charge of

about 15 nC. For an allowed droop of 150 mV, the required

bootstrap capacitance is 100 nF. Use an MLC capacitor.

A Schottky diode is recommended for the bootstrap diode due

to its low forward drop, which maximizes the drive available for

the high-side FET. The bootstrap diode must also be able to

withstand the maximum battery voltage plus 5 V. The average

forward current can be estimated by

I

Q

f

F AVG

GATE

MAX

(

×

(2)

Delay Resistor Selection

when the low-side FET drive turns off and when the high-side

drive starts to turn on. The delay resistor programs a specified

additional delay besides the 20 ns of fixed delay.

Printed Circuit Board Layout Considerations

Use the following general guidelines when designing printed

circuit boards:

1. Trace out the high current paths and use short, wide traces

to make these connections.

2. Locate the VCC bypass capacitor as close as possible to the

VCC and GND pins.

Rev. 6 | Page 9 of 10 | www.onsemi.com