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MT46V64M4 Datasheet(PDF) 1 Page - Micron Technology |
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MT46V64M4 Datasheet(HTML) 1 Page - Micron Technology |
1 / 93 page Products and specifications discussed herein are subject to change by Micron without notice. 256Mb: x4, x8, x16 DDR SDRAM Features PDF: 09005aef80768abb/Source: 09005aef82a95a3a Micron Technology, Inc., reserves the right to change products or specifications without notice. 256Mb_DDR_x4x8x16_D1.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN 1 ©2003 Micron Technology, Inc. All rights reserved. Double Data Rate (DDR) SDRAM MT46V64M4 – 16 Meg x 4 x 4 banks MT46V32M8 – 8 Meg x 8 x 4 banks MT46V16M16 – 4 Meg x 16 x 4 banks Features •VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V •VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (DDR400) • Bidirectional data strobe (DQS) transmitted/ received with data, that is, source-synchronous data capture (x16 has two – one per byte) • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle • Differential clock inputs (CK and CK#) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; center- aligned with data for WRITEs • DLL to align DQ and DQS transitions with CK • Four internal banks for concurrent operation • Data mask (DM) for masking write data (x16 has two – one per byte) • Programmable burst lengths (BL): 2, 4, or 8 •Auto refresh – 64ms, 8192-cycle(Commercial & Industrial) – 16ms, 8192-cycle (Automotive) • Self refresh (not available on AT devices) • Longer-lead TSOP for improved reliability (OCPL) • 2.5V I/O (SSTL_2-compatible) • Concurrent auto precharge option supported • tRAS lockout supported (tRAP = tRCD) Notes: 1. Only available on Revision F and G. 2. Only available on Revision K. 3. Not recommended for new designs. 4. Contact Micron for availability. Options Marking • Configuration – 64 Meg x 4 (16 Meg x 4 x 4 banks) 64M4 – 32 Meg x 8 (8 Meg x 8 x 4 banks) 32M8 – 16 Meg x 16 (4 Meg x 16 x 4 banks) 16M16 •Plastic package – OCPL – 66-pin TSOP TG – 66-pin TSOP (Pb-free) P •Plastic package – 60-ball FBGA (8mm x 14mm) FG1 – 60-ball FBGA (8mm x 14mm) (Pb-free) BG1 – 60-ball FBGA (8mm x 12.5mm) CV2 – 60-ball FBGA (8mm x 12.5mm) (Pb-free) CY2 • Timing – cycle time – 5ns @ CL = 3 (DDR400B) -5B – 6ns @ CL = 2.5 (DDR333) FBGA only -6 – 6ns @ CL = 2.5 (DDR333) TSOP only -6T – 7.5ns @ CL = 2 (DDR266) -75E1 – 7.5ns @ CL = 2 (DDR266A) -75Z1 – 7.5ns @ CL = 2.5 (DDR266B) -751 • Self refresh – Standard None – Low-power self refresh L • Temperature rating – Commercial (0°C to +70°C) None – Industrial (–40°C to +85°C) IT – Automotive (–40°C to +105°C) AT4 • Revision – x4, x8 :G3 – x16 :F3 – x4, x8, x16 :K |
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