CAT93C46R

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4

Table 8. INSTRUCTION SET

Instruction

Start Bit

Opcode

Address

Data

Comments

x8

x16

x8

x16

READ

1

10

A6−A0

A5−A0

Read Address AN–A0

ERASE

1

11

A6−A0

A5−A0

Clear Address AN–A0

WRITE

1

01

A6−A0

A5−A0

D7−D0

D15−D0

Write Address AN–A0

EWEN

1

00

11XXXXX

11XXXX

Write Enable

EWDS

1

00

00XXXXX

00XXXX

Write Disable

ERAL

1

00

10XXXXX

10XXXX

Clear All Addresses

WRAL

1

00

01XXXXX

01XXXX

D7−D0

D15−D0

Write All Addresses

Device Operation

The CAT93C46R is a 1024−bit nonvolatile memory

intended for use with industry standard microprocessors.

The CAT93C46R can be organized as either registers of 16

bits or 8 bits. When organized as X16, seven 9−bit

instructions control the reading, writing and erase

operations of the device. When organized as X8, seven

10−bit instructions control the reading, writing and erase

operations of the device. The CAT93C46R operates on a

single power supply and will generate on chip the high

voltage required during any write operation.

Instructions, addresses, and write data are clocked into the

DI pin on the rising edge of the clock (SK). The DO pin is

normally in a high impedance state except when reading data

from the device, or when checking the ready/busy status

after a write operation.

The ready/busy status can be determined after the start of

a write operation by selecting the device (CS high) and

polling the DO pin; DO low indicates that the write

operation is not completed, while DO high indicates that the

device is ready for the next instruction. If necessary, the DO

pin may be placed back into a high impedance state during

chip select by shifting a dummy “1” into the DI pin. The DO

pin will enter the high impedance state on the rising edge of

the clock (SK). Placing the DO pin into the high impedance

state is recommended in applications where the DI pin and

the DO pin are to be tied together to form a common DI/O

pin. The Ready/Busy flag can be disabled only in Ready

state; no change is allowed in Busy state.

The format for all instructions sent to the device is a

logical “1” start bit, a 2−bit (or 4−bit) opcode, 6−bit address

(an additional bit when organized X8) and for write

operations a 16−bit data field (8−bit for X8 organization).

Read

Upon receiving a READ command and an address

(clocked into the DI pin), the DO pin of the CAT93C46R will

come out of the high impedance state and, after sending an

initial dummy zero bit, will begin shifting out the data

addressed (MSB first). The output data bits will toggle on

the rising edge of the SK clock and are stable after the

Sequential Read

After the 1st data word has been shifted out and CS

remains asserted with the SK clock continuing to toggle, the

CAT93C46R will automatically increment to the next

address and shift out the next data word. As long as CS is

continuously asserted and SK continues to toggle, the device

will keep incrementing to the next address automatically

until it reaches the end of the address space, then loops back

to address 0. In the sequential Read mode, only the initial

data word is preceeded by a dummy zero bit; all subsequent

data words will follow without a dummy zero bit.

Erase/Write Enable and Disable

The CAT93C46R powers up in the write disable state.

Any writing after power−up or after an EWDS (write

disable) instruction must first be preceded by the EWEN

(write enable) instruction. Once the write instruction is

enabled, it will remain enabled until power to the device is

removed, or the EWDS instruction is sent. The EWDS

instruction can be used to disable all CAT93C46R write and

erase instructions, and will prevent any accidental writing or

clearing of the device. Data can be read normally from the

device regardless of the write enable/disable status.