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CAT5419WI50 Datasheet(PDF) 8 Page - ON Semiconductor |
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CAT5419WI50 Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 16 page CAT5419 Doc. No. MD-2115 Rev. J 8 2009 SCILLC. All rights reserved. Characteristics subject to change without notice INSTRUCTIONS AND REGISTER DESCRIPTION INSTRUCTIONS Slave Address Byte The first byte sent to the CAT5419 from the master/ processor is called the Slave/DPP Address Byte. The most significant four bits of the slave address are a device type identifier. These bits for the CAT5419 are fixed at 0101[B] (refer to Table 1). The next four bits, A3 - A0, are the internal slave address and must match the physical device address which is defined by the state of the A3 - A0 input pins for the CAT5419 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A3 - A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. Instruction Byte The next byte sent to the CAT5419 contains the instruction and register pointer information. The four most significant bits used provide the instruction opcode I [3:0]. The R1 and R0 bits point to one of the four data registers of each associated potentiometer. The least two significant bits point to one of two Wiper Control Registers. The format is shown in Table 2. Data Register Selection Data Register Selected R1 R0 DR0 0 0 DR1 0 1 DR2 1 0 DR3 1 1 Table 1. Identification Byte Format Table 2. Instruction Byte Format ID3 ID2 ID1 ID0 A3 A2 A1 A0 0101 (MSB) (LSB) Device Type Identifier Slave Address I3 I2 I1 I0 R1 R0 0 P0 (MSB) (LSB) WCR/Pot Selection Instruction Opcode Data Register Selection |
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