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CAT9532WI Datasheet(PDF) 10 Page - ON Semiconductor |
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CAT9532WI Datasheet(HTML) 10 Page - ON Semiconductor |
10 / 18 page CAT9532 Write Operations Data is transmitted to the CAT9532 registers using the write sequence shown in Figure 6. If the AI bit from the command byte is set to “1”, the CAT9532 internal registers can be written sequentially. After sending data to one register, the next data byte will be sent to the next register sequentially addressed. Read Operations The CAT9532 registers are read according to the timing diagrams shown in Figure 7 and Figure 8. Data from the register, defined by the command byte, will be sent serially on the SDA line. After the first byte is read, additional data bytes may be read when the auto-increment flag, AI, is set. The additional data byte will reflect the data read from the next register sequentially addressed by the (B3 B2 B1 B0) bits of the command byte. When reading Input Port Registers (Figure 8), data is clocked into the register on the failing edge of the acknowledge clock pulse. The transfer is stopped when the master will not acknowledge the data byte received and issue the STOP condition. LED Pins Used as General Purpose I/O Any LED pins not used to drive LEDs can be used as general purpose input/output, GPIO. When used as input, the user should program the corresponding LED pin to Hi-Z (“00” for the LSx register bits). The pin state can be read via the Input Register according to the sequence shown in Figure 8. For use as output, an external pull-up resistor should be connected to the pin. The value of the pull-up resistor is calculated according to the DC operating characteristics. To set the LED output high, the user has to program the output Hi-Z writing “00” into the corresponding LED Selector (LSx) register bits. The output pin is set low when the LED output is programmed low through the LSx register bits (“01” in LSx register bits). Figure 6. Write to Register Timing Diagram Figure 7. Read from Register Timing Diagram 12 SCL WRITE TO REGISTER DATA OUT FROM PORT 34 5 6 7 8 SDA A Slave Address Data To Register 1 Start Condition R/W Acknowledge From Slave Acknowledge From Slave Acknowledge From Slave 9 Command Byte 1.0 A Data To Register 2 S 1 1 0 0 A2 A1 A0 0 tpv A A AI B3 B2 B1 B0 A 00 0 DAT 1 S A 0 0 A2 A1 A0 1 1 0 0 A2 A1 A0 1 1 A A COMMAND BYTE Acknowledge From Slave Acknowledge Acknowledge From Slave Acknowledg From Slave A P NA e From Master S DATA DATA R/W First Byte Last Byte No Acknowledge From Master 1 Slave Address Data From Register Data From Register Slave Address MSB LSB MSB LSB 0 Note: Transfer can be stopped at any time by a STOP condition. R/W At This Moment Master-Transmitter Becomes Master-receiver and Slave-Receiver Becomes Slave-Transmitter Auto-increment Register Address If Al = 1 Doc. No. MD-9001 Rev. E 10 © 2010 SCILLC. All rights reserved Characteristics subject to change without notice |
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