CAT9532HT6I-G datasheet(7/18 Pages) ONSEMI

Part #	CAT9532HT6I-G

Description	16-bit Programmable LED Dimmer with I2C Interface

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CAT9532

FUNCTIONAL DESCRIPTION

The CAT9532 is a 16-bit I/O bus expander that

provides a programmable LED dimmer, controlled

through an I

2C compatible serial interface.

The CAT9532 supports the I

2C Bus data transmission

protocol. This Inter-Integrated Circuit Bus protocol

defines any device that sends data to the bus to be a

transmitter and any device receiving data to be a

receiver. The transfer is controlled by the Master

device which generates the serial clock and all

START and STOP conditions for bus access. The

CAT9532 operates as a Slave device. Both the

Master device and Slave device can operate as either

transmitter or receiver, but the Master device controls

which mode is activated.

I

2C Bus Protocol

The features of the I

2C bus protocol are defined as

follows:

(1) Data transfer may be initiated only when the bus

is not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock line is

high will be interpreted as a START or STOP

condition (Figure 2).

START and STOP Conditions

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT9532 monitors the

SDA and SCL lines and will not respond until this

condition is met.

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must

end with a STOP condition.

Device Addressing

After the bus Master sends a START condition, a

slave address byte is required to enable the CAT9532

for a read or write operation. The four most significant

bits of the slave address are fixed as binary 1100

(Figure 3). The CAT9532 uses the next three bits as

address bits.

The address bits A2, A1 and A0 are used to select

which device is accessed from maximum eight

devices on the same bus. These bits must compare to

their hardwired input pins. The 8th bit following the 7-

bit slave address is the R/W bit that specifies whether

a read or write operation is to be performed. When

this bit is set to “1”, a read operation is initiated, and

when set to “0”, a write operation is selected.

Following the START condition and the slave address

byte, the CAT9532 monitors the bus and responds

with an acknowledge (on the SDA line) when its

address matches the transmitted slave address. The

CAT9532 then performs a read or a write operation

depending on the state of the R/W bit.

Figure 2. Start/Stop Timing

START CONDITION

SDA

STOP CONDITION

SCL

Figure 3. CAT9532 Slave Address

1

10

0

A2

A1

A0

R/W

SLAVE ADDRESS

FIXED

PROGRAMMABLE

HARDWARE

SELECTABLE

7

Doc. No. MD-9001 Rev. E

Characteristics subject to change without notice

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CAT9532HT6I-G Datasheet(PDF) 7 Page - ON Semiconductor

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