CAT9555HT6I-G datasheet(11/18 Pages) ONSEMI

Part #	CAT9555HT6I-G

Description	16-bit I짼C and SMBus I/O Port with Interrupt

Download	18 Pages

Scroll/Zoom	100%

Manufacturer	ONSEMI [ON Semiconductor]

Direct Link	http://www.onsemi.com

Logo

11 / 18 page

CAT9555

The output port register sets the outgoing logic levels

of the I/O ports, defined as outputs by the configu-

ration register. Bit values in this register have no effect

on I/O pins defined as inputs. Reads from the output

port register reflect the value that is in the flip-flop

controlling the output, not the actual I/O pin value.

The polarity inversion register allows the user to invert

the polarity of the input port register data. If a bit in

this register is set (“1”) the corresponding input port

data is inverted. If a bit in the polarity inversion

register is cleared (“0”), the original input port polarity

is retained.

The configuration register sets the directions of the

ports. Set the bit in the configuration register to enable

the corresponding port pin as an input with a high

impedance output driver. If a bit in this register is

cleared, the corresponding port pin is enabled as an

output. At power-up, the I/Os are configured as inputs

with a weak pull-up resistor to VCC.

Writing to the Port Registers

Data is transmitted to the CAT9555 registers using the

write mode shown in Figure 8 and Figure 9.

The CAT9555 registers are configured to operate at

four register pairs: Input Ports, Output Ports, Polarity

Inversion Ports and Configuration Ports. After sending

data to one register, the next data byte will be sent to

the other register in the pair. For example, if the first

byte of data is sent to the Configuration Port 1

(register 7), the next byte will be stored in the

Configuration Port 0 (register 6). Each 8-bit register

may be updated independently of the other registers.

Reading the Port Registers

The CAT9555 registers are read according to the

timing diagrams shown in Figure 10 and Figure 11.

Data from the register, defined by the command byte,

will be sent serially on the SDA line. Data is clocked

into the register on the failing edge of the

acknowledge clock pulse. After the first byte is read,

additional data bytes may be read, but the second

read will reflect the data from the other register in the

pair. For example, if the first read is data from Input

Port 0, the next read data will be from Input Port 1.

The transfer is stopped when the master will not

acknowledge the data byte received and issue the

STOP condition.

12

SCL

WRITE TO

PORT

DATA OUT

FROM PORT 0

34

5

6

7

8

SDA

A

slave address

data to port 0

start condition

R/W acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

tpv

9

command byte

DATA 1

1.7

1.0

A

data to port 1

S

0

1

0

A2 A1 A0

0

DATA OUT

FROM PORT 1

DATA VALID

tpv

P

A

0

00

0

00

DAT

0

1

0.7

0.0

stop

condition

Figure 8. Write to Output Port Register

Characteristics subject to change without notice

Figure 9. Write to Configuration Register

12

SCL

34

5

67

8

SDA

AA

A

DATA 0

slave address

data to configuration 0

start condition

R/W acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

9

0

00

0

1

command byte

MSB

LSB

DATA 1

MSB

LSB A

data to configuration 1

S

0

1

0

A2 A1 A0

0

12

3

4

5

6

7

89

12

34

5

6

789

12

3

4

5

A

P

11

Doc. No. MD-9003, Rev. J

Similar Part No. - CAT9555HT6I-G

Manufacturer	Part #	Datasheet	Description
ON Semiconductor	CAT9555HT6I-G	176Kb / 16P	16-bit I2C and SMBus I/O Port with Interrupt June, 2011 ??Rev. 11
ON Semiconductor	CAT9555HT6I-GT2	176Kb / 16P	16-bit I2C and SMBus I/O Port with Interrupt June, 2011 ??Rev. 11

More results

Similar Description - CAT9555HT6I-G

Manufacturer	Part #	Datasheet	Description
ON Semiconductor	CAT9555WI	201Kb / 17P	16-bit I짼C and SMBus I/O Port with Interrupt Doc. No. MD-9003, Rev. I
	CAT9534	172Kb / 16P	8-bit I짼C and SMBus I/O Port with Interrupt Doc. No. MD-9004 Rev. D
	CAT9554WI-G	184Kb / 16P	8-bit I짼C and SMBus I/O Port with Interrupt Doc. No. MD-9002, Rev. F
	CAT9534WI-G	244Kb / 16P	8-bit I짼C and SMBus I/O Port with Interrupt Doc. No. MD-9004 Rev. C
	CAT9554	209Kb / 16P	8-bit I짼C and SMBus I/O Port with Interrupt Doc. No. MD-9002, Rev. F
Catalyst Semiconductor	CAT9555	212Kb / 17P	16-bit I2C and SMBus I/O Port with Interrupt
NXP Semiconductors	PCA9555	185Kb / 22P	16-bit I2C and SMBus I/O port with interrupt 2004 Sep 30
Catalyst Semiconductor	CAT9555	235Kb / 17P	16-bit I2C and SMBus I/O Port with Interrupt
ON Semiconductor	CAT9555	176Kb / 16P	16-bit I2C and SMBus I/O Port with Interrupt June, 2011 ??Rev. 11
NXP Semiconductors	PCA9555	583Kb / 34P	16-bit I2C-bus and SMBus I/O port with interrupt Rev. 08-22 October 2009

More results

CAT9555HT6I-G Datasheet(PDF) 11 Page - ON Semiconductor

CAT9555HT6I-G Datasheet(HTML) 11 Page - ON Semiconductor

Similar Part No. - CAT9555HT6I-G

Similar Description - CAT9555HT6I-G

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datasheet Download

Link URL