CAT9554AHV4I-GT2 datasheet(8/16 Pages) ONSEMI

Part #	CAT9554AHV4I-GT2

Description	8-bit I짼C and SMBus I/O Port with Interrupt

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CAT9554, CAT9554A

Doc. No. MD-9002 Rev. F

8

Characteristics subject to change without notice

FUNCTIONAL DESCRIPTION

The CAT9554 and CAT9554A general purpose input/

output (GPIO) peripherals provide up to eight I/O

ports, controlled through an I²C compatible serial

interface

The

CAT9554/54A

support

the

I²C

Bus

data

transmission protocol. This I²C Bus protocol defines

any device that sends data to the bus to be a

transmitter and any device receiving data to be a

receiver. The transfer is controlled by the Master

device which generates the serial clock and all

START and STOP conditions for bus access. The

CAT9554/9554A operate as a Slave device. Both the

Master device and Slave device can operate as either

transmitter or receiver, but the Master device controls

which mode is activated.

I²C BUS PROTOCOL

The features of the I²C bus protocol are defined as

follows:

(1) Data transfer may be initiated only when the bus

is not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock line is

high will be interpreted as a START or STOP

condition (Figure 5).

START AND STOP CONDITIONS

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT9554/9554A

monitors the SDA and SCL lines and will not respond

until this condition is met.

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must

end with a STOP condition.

DEVICE ADDRESSING

After the bus Master sends a START condition, a slave

address byte is required to enable the CAT9554/9554A

for a read or write operation. The four most significant

bits of the slave address are fixed as binary 0100 for

the CAT9554 (Figure 6) and as 0111 for the CAT9554A

(Figure 7). The CAT9554/9554A uses the next three

bits as address bits.

The address bits A2, A1 and A0 are used to select

which device is accessed from maximum eight

devices on the same bus. These bits must compare to

their hardwired input pins. The 8th bit following the 7-

bit slave address is the R/W

¯¯ bit that specifies whether

a read or write operation is to be performed. When

this bit is set to “1”, a read operation is initiated, and

when set to “0”, a write operation is selected.

Following the START condition and the slave address

byte, the CAT9554/9554A monitors the bus and

responds with an acknowledge (on the SDA line) when

its address matches the transmitted slave address. The

CAT9554/9554A then performs a read or a write

operation depending on the state of the R/W

¯¯ bit.

Figure 5. START/STOP Condition

Figure 6. CAT9554 Slave Address

Figure 7. CAT9554A Slave Address

0

1

0

A2A1A0

R/W

SLAVE ADDRESS

FIXED

PROGRAMMABLE

HARDWARE

SELECTABLE

0

1

A2A1A0

R/W

SLAVE ADDRESS

FIXED

PROGRAMMABLE

HARDWARE

SELECTABLE

START

CONDITION

STOP

CONDITION

SDA

SCL

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CAT9554AHV4I-GT2 Datasheet(PDF) 8 Page - ON Semiconductor

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