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MC9S08GB32A Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc |
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MC9S08GB32A Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc |
4 / 302 page MC9S08GB60A Data Sheet, Rev. 2 6 Freescale Semiconductor Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. Revision Number Revision Date Description of Changes 1.00 07/14/2005 Initial public release. 1.01 09/04/2007 Added a footnote to RTI of Table 3.2; Added RTI description to Section 3.5.6; Added a sentence "If active BDM mode is enabled in stop3, the internal RTI clock is not available." to the Section 5.7 Real Time Interrupt. 1.02 02/25/2008 Changed the Maximun Low Power of FBE and FEE in Table A-9 to 10 MHz. Changed the Title of Table 13-2 from “IIC1A Register Field Descriptions” to “IIC1F Register Field Descriptions” 2 7/30/2008 Added 42-pin SDIP information. Changed “However, when HGO=0, the maximum frequency is 8 MHz in FEE and FBE modes.” to “However, when HGO=0, the maximum frequency is 10 MHz in FEE and FBE modes.” in Appendix B5. Updated the “How to reach us” at backpage. This product incorporates SuperFlash® technology licensed from SST. Freescale‚ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2005-2008. All rights reserved. |
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