 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
M34E02-FMB6P Datasheet(PDF) 9 Page - STMicroelectronics |
|
||||||||||||||||||||||||||||||
M34E02-FMB6P Datasheet(HTML) 9 Page - STMicroelectronics |
|
|
9 / 34 page  M34E02, M34E02-F Signal description Doc ID 10367 Rev 10 9/34 2.5 Supply voltage (VCC) 2.5.1 Operating supply voltage VCC Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 8). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). 2.5.2 Power-up conditions The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in Table 8 and the rise time must not vary faster than 1 V/µs. 2.5.3 Device reset In order to prevent inadvertent write operations during power-up, a power-on reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the internal reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 8). When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode. However, the device must not be accessed until VCC reaches a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range. In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops below the power-on reset threshold voltage, the device stops responding to any instruction sent to it. 2.5.4 Power-down conditions During power-down (continuous decrease in VCC), the device must be in Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress). Figure 4. Maximum RP value versus bus parasitic capacitance (C) for an I 2C bus 1 10 100 10 100 1000 Bus line capacitor (pF) When tLOW = 1.3 µs (min value for fC = 400 kHz), the Rbus × Cbus time constant must be below the 400 ns time constant line represented on the left. I²C bus master M24xxx Rbus VCC Cbus SCL SDA ai14796b R bus × C bus = 400 ns Here Rbus × Cbus = 120 ns 4 k Ω 30 pF |
Similar Part No. - M34E02-FMB6P |
|
Similar Description - M34E02-FMB6P |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
