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SC9S12XS256J1VAAR Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc |
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SC9S12XS256J1VAAR Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc |
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2 / 738 page  To provide the most up-to-date information, the document revision on the World Wide Web is the most current. A printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ This document contains information for the complete S12XS Family and thus includes a set of separate flash (FTMR) module sections to cover the whole family. A full list of family members and options is included in the appendices. This document contains information for all constituent modules, with the exception of the CPU. For CPU information please refer to CPU12XV1 in the CPU12/CPU12X Reference Manual. Revision History Date Revision Level Description May, 2009 1.08 Removed all KGD references Corrected Detailed Register Map (FERSTAT) Corrected statement on VDDA/VDDX protection diodes September, 2009 1.09 Updated Chapter 8 S12XE Clocks and Reset Generator (S12XECRGV1) Updated Chapter 14 Serial Communication Interface (S12SCIV5) Updated Chapter 16 Timer Module (TIM16B8CV2) Updated Chapter 18 256 KByte Flash Module (S12XFTMR256K1V1) Updated Chapter 19 128 KByte Flash Module (S12XFTMR128K1V1) Updated Chapter 20 64 KByte Flash Module (S12XFTMR64K1V1) May, 2010 1.10 Updated Chapter 2 Port Integration Module (S12XSPIMV1) Updated Chapter 16 Timer Module (TIM16B8CV2) BDM Alternate clock source defined in device overview |
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