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1779ES–ATARM–14-Apr-06

AT91M42800A

7.

Product Overview

7.1

Power Supply

The AT91M42800A has three kinds of power supply pins:

• VDDCORE pins, which power the chip core

• VDDIO pins, which power the I/O lines

• VDDPLL pins, which power the oscillator and PLL cells

VDDCORE and VDDIO pins allow core power consumption to be reduced by supplying it with a

lower voltage than the I/O lines. The VDDCORE pins must never be powered at a voltage

greater than the supply voltage applied to the VDDIO.

The VDDPLL pin is used to supply the oscillator and both PLLs. The voltage applied on these

pins is typically 3.3V, and it must not be lower than VDDCORE.

Typical supported voltage combinations are shown in the following table:

7.2

Input/Output Considerations

After the reset, the peripheral I/Os are initialized as inputs to provide the user with maximum

flexibility. It is recommended that in any application phase, the inputs to the AT91M42800A

microcontroller be held at valid logic levels to minimize the power consumption.

7.3

Operating Modes

The AT91M42800A has two pins dedicated to defining MODE0 and MODE1 operating modes.

These pins allow the user to enter the device in Boundary Scan mode. They also allow the user

to run the processor from the on-chip oscillator and from an external clock by bypassing the on-

chip oscillator. The last mode is reserved for test purposes. A chip reset must be performed

(NRST and NTRST) after MODE0 and/or MODE1 have been changed.

7.4

Clock Generator

The AT91M42800A microcontroller embeds a 32.768 kHz oscillator that generates the Slow

Clock (SLCK). This on-chip oscillator can be bypassed by setting the correct logical level on

MODE0 and MODE1 pins, as shown above. In this case, SLCK equals XIN.

Pins

Nominal Supply Voltages

VDDCORE

3.3V

3.0V or 3.3V

VDDIO

5.0V

3.0V or 3.3V

VDDPLL

3.3V

3.0V or 3.3V

MODE0

MODE1

Operating Mode

0

0

Normal operating mode by using the on-chip oscillator

0

1

Boundary Scan Mode

1

0

Normal operating mode by using an external clock on XIN

1

1

Reserved for test