10

6254CS–ATARM–08-Jan-10

AT91SAM9XE128/256/512 Preliminary

Notes:

1. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all

the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Inter-

face signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the

peripheral multiplexing tables.

2. Refer to PIO Multiplexing (see Section 10.3 “Peripheral Signals Multiplexing on I/O Lines”).

Ethernet 10/100

ETXCK

Transmit Clock or Reference Clock

Input

VDDIOP0

MII only, REFCK in RMII

ERXCK

Receive Clock

Input

VDDIOP0

MII only

ETXEN

Transmit Enable

Output

VDDIOP0

ETX0-ETX3

Transmit Data

Output

VDDIOP0

ETX0-ETX1 only in RMII

ETXER

Transmit Coding Error

Output

VDDIOP0

MII only

ERXDV

Receive Data Valid

Input

VDDIOP0

RXDV in MII, CRSDV in RMII

ERX0-ERX3

Receive Data

Input

VDDIOP0

ERX0-ERX1 only in RMII

ERXER

Receive Error

Input

VDDIOP0

ECRS

Carrier Sense and Data Valid

Input

VDDIOP0

MII only

ECOL

Collision Detect

Input

VDDIOP0

MII only

EMDC

Management Data Clock

Output

VDDIOP0

EMDIO

Management Data Input/Output

I/O

VDDIOP0

EF100

Force 100Mbit/sec.

Output

High

VDDIOP0

Image Sensor Interface

ISI_D0-ISI_D11

Image Sensor Data

Input

VDDIOP1

ISI_MCK

Image sensor Reference clock

output

VDDIOP1

ISI_HSYNC

Image Sensor Horizontal Synchro

input

VDDIOP1

ISI_VSYNC

Image Sensor Vertical Synchro

input

VDDIOP1

ISI_PCK

Image Sensor Data clock

input

VDDIOP1

Analog to Digital Converter

AD0-AD3

Analog Inputs

Analog

VDDANA

Digital pulled-up inputs at reset

ADVREF

Analog Positive Reference

Analog

VDDANA

ADTRG

ADC Trigger

Input

VDDANA

Fast Flash Programming Interface

PGMEN[3:0]

Programming Enabling

Input

VDDIOP0

PGMNCMD

Programming Command

Input

Low

VDDIOP0

PGMRDY

Programming Ready

Output

High

VDDIOP0

PGMNOE

Programming Read

Input

Low

VDDIOP0

PGMNVALID

Data Direction

Output

Low

VDDIOP0

PGMM[3:0]

Programming Mode

Input

VDDIOP0

PGMD[15:0]

Programming Data

I/O

VDDIOP0

Table 3-1.

Signal Description List (Continued)

Signal Name

Function

Type

Active

Level

Reference

Voltage

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