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MC56F8006 Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc |
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MC56F8006 Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc |
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4 / 100 page  MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Block Diagram Freescale Semiconductor 4 2 Block Diagram Figure 1shows a top-level block diagram of the MC56F8006/MC56F8002 digital signal controller. Package options for this family are described later in this document. Italics indicate a 56F8002 device parameter. Figure 1. MC56F8006/MC56F8002 Block Diagram 3 Overview 3.1 56F8006/56F8002 Features 3.1.1 Core • Efficient 16-bit 56800E family digital signal controller (DSC) engine with dual Harvard architecture • As many as 32 million instructions per second (MIPS) at 32 MHz core frequency • 155 basic instructions in conjunction with up to 20 address modes • Single-cycle 16 × 16-bit parallel multiplier-accumulator (MAC) • Four 36-bit accumulators, including extension bits • 32-bit arithmetic and logic multi-bit shifter Program Controller and Hardware Looping Unit Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators Address Generation Unit Bit Manipulation Unit 16-Bit 56800E Core Interrupt Controller 4 Unified Data / Program RAM 2KB PDB CDBR SPI IPBus Bridge R/W Control Memory PAB CDBW JTAG/EOnCE Port or GPIOD Digital Reg Analog Reg Low-Voltage Supervisor VDD VSS VDDA VSSA 4 RESET 6 Dual GP Timer ADCA 4 24 Total Clock Generator* System Integration Module ROSC PWM Outputs PWM COP/ Watchdog ADCB Flash Memory 16 Kbytes flash 12 Kbytes flash PGA/ADC SCI 2 3 CMP0 2 CMP2 2 CMP or GPIOD CMP1 2 Crystal Oscillator Power Management Controller programmable I2C 2 PIT delay block 3 40 GPIO are muxed with all other func pins. PMC 3 Fault Inputs PDB XAB1 XAB2 System Bus Control PAB CDBR CDBW XDB2 OSC RTC Note: All pins are muxed with other peripheral pins. 2 |
Similar Part No. - MC56F8006 |
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Similar Description - MC56F8006 |
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