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MC56F8002VWL Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc |
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MC56F8002VWL Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc |
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7 / 100 page  Overview MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor 7 • One serial peripheral interface (SPI) — Full-duplex operation — Master and slave modes — Programmable length transactions (2 to 16 bits) — Programmable transmit and receive shift order (MSB as first or last bit transmitted) — Maximum slave module frequency = module clock frequency/2 • One inter-integrated Circuit (I2C) port — Operates up to 400 kbps — Supports master and slave operation — Supports 10-bit address mode and broadcasting mode — Supports SMBus, Version 2 • One 16-bit programmable interval timer (PIT) — 16 bit counter with programmable counter modulo — Interrupt capability • One 16-bit programmable delay block (PDB) — 16 bit counter with programmable counter modulo and delay time — Counter is initiated by positive transition of internal or external trigger pulse — Supports two independently controlled delay pulses used to synchronize PGA and ADC conversions with input trigger event — Two PDB outputs can be ORed together to schedule two conversions from one input trigger event — PDB outputs can be can be used to schedule precise edge placement for a pulsed output that generates the control signal for the CMP windowing comparison — Supports continuous or single shot mode — Bypass mode supported • Computer operating properly (COP)/watchdog timer capable of selecting different clock sources — Programmable prescaler and timeout period — Programmable wait, stop, and partial powerdown mode operation — Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected — Choice of clock sources from four sources in support of EN60730 and IEC61508: – On-chip relaxation oscillator – External crystal oscillator/external clock source – System clock (IPBus up to 32 MHz) – On-chip low power 1 kHz oscillator • Real-timer counter (RTC) — 8-bit up-counter — Three software selectable clock sources – External crystal oscillator/external clock source – On-chip low-power 1 kHz oscillator – System bus (IPBus up to 32 MHz) — Can signal the device to exit power down mode • Phase lock loop (PLL) provides a high-speed clock to the core and peripherals — Provides 3x system clock to PWM and dual timer and SCI — Loss of lock interrupt — Loss of reference clock interrupt • Clock sources |
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Similar Description - MC56F8002VWL |
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