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56F8346 Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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56F8346 Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
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6 / 178 page  56F8346 Technical Data, Rev. 15 6 Freescale Semiconductor Preliminary Part 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 56F8346/56F8146 Features . . . . . . . . . . . . 7 1.2 Device Description. . . . . . . . . . . . . . . . . . . . 9 1.3 Award-Winning Development Environment . . . . . . . . . . . . . . . . . . . 11 1.4 Architecture Block Diagram . . . . . . . . . . . . 11 1.5 Product Documentation . . . . . . . . . . . . . . . 15 1.6 Data Sheet Conventions . . . . . . . . . . . . . . 16 Part 2 Signal/Connection Descriptions . . . . 17 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . . 20 Part 3 On-Chip Clock Synthesis (OCCS) . . . 40 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . 40 3.2 External Clock Operation. . . . . . . . . . . . . . 40 3.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Part 4 Memory Map . . . . . . . . . . . . . . . . . . . . 42 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . 42 4.2 Program Map . . . . . . . . . . . . . . . . . . . . . . . 44 4.3 Interrupt Vector Table . . . . . . . . . . . . . . . . 45 4.4 Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.5 Flash Memory Map . . . . . . . . . . . . . . . . . . 49 4.6 EOnCE Memory Map. . . . . . . . . . . . . . . . . 51 4.7 Peripheral Memory Mapped Registers . . . 52 4.8 Factory Programmed Memory . . . . . . . . . . 79 Part 5 Interrupt Controller (ITCN) . . . . . . . . . 79 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3 Functional Description . . . . . . . . . . . . . . . . 80 5.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 81 5.5 Operating Modes . . . . . . . . . . . . . . . . . . . . 81 5.6 Register Descriptions. . . . . . . . . . . . . . . . . 82 5.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Part 6 System Integration Module (SIM) . . 109 6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.3 Operating Modes . . . . . . . . . . . . . . . . . . . 111 6.4 Operating Mode Register. . . . . . . . . . . . . 111 6.5 Register Descriptions. . . . . . . . . . . . . . . . 112 6.6 Clock Generation Overview . . . . . . . . . . . 125 6.7 Power-Down Modes Overview . . . . . . . . 125 6.8 Stop and Wait Mode Disable Function . . 126 6.9 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Part 7 Security Features . . . . . . . . . . . . . . . 127 7.1 Operation with Security Enabled . . . . . . . 127 7.2 Flash Access Blocking Mechanisms . . . . 127 Part 8 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 130 8.2 Memory Maps . . . . . . . . . . . . . . . . . . . . . 130 8.3 Configuration . . . . . . . . . . . . . . . . . . . . . . 130 Part 9 Joint Test Action Group (JTAG) . . 136 9.1 JTAG Information . . . . . . . . . . . . . . . . . . 136 Part 10 Specifications . . . . . . . . . . . . . . . . 136 10.1 General Characteristics. . . . . . . . . . . . . . 136 10.2 DC Electrical Characteristics. . . . . . . . . . 141 10.3 AC Electrical Characteristics . . . . . . . . . . 145 10.4 Flash Memory Characteristics. . . . . . . . . 145 10.5 External Clock Operation Timing . . . . . . 146 10.6 Phase Locked Loop Timing. . . . . . . . . . . 146 10.7 Crystal Oscillator Timing . . . . . . . . . . . . . 147 10.8 External Memory Interface Timing . . . . . 147 10.9 Reset, Stop, Wait, Mode Select, and Interrupt Timing . . . . . . . . . . . . . . . 150 10.10 Serial Peripheral Interface (SPI) Timing. . . . . . . . . . . . . . . . . . . . . . . 152 10.11 Quad Timer Timing . . . . . . . . . . . . . . . . . 157 10.12 Quadrature Decoder Timing . . . . . . . . . . 157 10.13 Serial Communication Interface (SCI) Timing. . . . . . . . . . . . . . . . . . . . . . . 158 10.14 Controller Area Network (CAN) Timing . . 159 10.15 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . 159 10.16 Analog-to-Digital Converter (ADC) Parameters . . . . . . . . . . . . . . . . . . . 161 10.17 Equivalent Circuit for ADC Inputs . . . . . . 163 10.18 Power Consumption . . . . . . . . . . . . . . . . 165 Part 11 Packaging . . . . . . . . . . . . . . . . . . . 167 11.1 56F8346 Package and Pin-Out Information . . . . . . . . . . . . . . . . . . . 167 11.2 56F8146 Package and Pin-Out Information . . . . . . . . . . . . . . . . . . . 169 Part 12 Design Considerations . . . . . . . . . 174 12.1 Thermal Design Considerations . . . . . . . 174 12.2 Electrical Design Considerations . . . . . . 175 12.3 Power Distribution and I/O Ring Implementation . . . . . . . . . . . . . . . . 176 Part 13 Ordering Information . . . . . . . . . . 177 Table of Contents |
Similar Part No. - 56F8346_07 |
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Similar Description - 56F8346_07 |
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