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56F803 Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc |
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56F803 Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc |
8 / 52 page 56F803 Technical Data, Rev. 16 8 Freescale Semiconductor Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F803 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2 through Table 2-17, each table row describes the signal or signals present on a pin. Table 2-1 Functional Group Pin Allocations Functional Group Number of Pins Detailed Description Power (VDD or VDDA)7 Table 2-2 Ground (VSS or VSSA)7 Table 2-3 Supply Capacitors 2 Table 2-4 PLL and Clock 3 Table 2-5 Address Bus1 16 Table 2-6 Data Bus 16 Table 2-7 Bus Control 4 Table 2-8 Interrupt and Program Control 4 Table 2-9 Pulse Width Modulator (PWM) Port 12 Table 2-10 Serial Peripheral Interface (SPI) Port1 1. Alternately, GPIO pins 4 Table 2-11 Quadrature Decoder Port2 2. Alternately, Quad Timer pins 4 Table 2-12 Serial Communications Interface (SCI) Port1 2 Table 2-13 CAN Port 2 Table 2-14 Analog to Digital Converter (ADC) Port 9 Table 2-15 Quad Timer Module Port 2 Table 2-16 JTAG/On-Chip Emulation (OnCE) 6 Table 2-17 |
Similar Part No. - 56F803_07 |
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Similar Description - 56F803_07 |
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