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DSP56F805 Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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DSP56F805 Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
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3 / 56 page  56F805 Technical Data, Rev. 16 Freescale Semiconductor 3 56F805 Block Diagram JTAG/ OnCE Port Digital Reg Analog Reg Low Voltage Supervisor Program Controller and Hardware Looping Unit Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers Two 36-bit Accumulators Address Generation Unit Bit Manipulation Unit PLL Clock Gen 16-Bit 56800 Core PAB PDB XDB2 CGDB XAB1 XAB2 XTAL EXTAL INTERRUPT CONTROLS IPBB CONTROLS IPBus Bridge (IPBB) MODULE CONTROLS ADDRESS BUS [8:0] DATA BUS [15:0] COP RESET RESET IRQA IRQB Applica- tion-Specific Memory & Peripherals Interrupt Controller Program Memory 32252 x 16 Flash 512 x 16 SRAM Boot Flash 2048 x 16 Flash Data Memory 4096 x 16 Flash 2048 x 16 SRAM COP/ Watchdog SPI or GPIO SCI0 or GPIO Quad Timer D / Alt Func Quad Timer C A/D1 A/D2 ADC 4 2 4 4 4 4 6 PWM Outputs Fault Inputs PWMA 16 16 VCAPC VDD VSS VDDA VSSA 6 28 8* • • • • • • • • EXTBOOT Current Sense Inputs 3 Quadrature Decoder 0/ Quad Timer A CAN 2.0A/B 2 CLKO External Address Bus Switch Bus Control External Data Bus Switch External Bus Interface Unit RD Enable WR Enable DS Select PS Select 10 16 6 A[00:05] D[00:15] A[06:15] or GPIO-E2:E3 & GPIO-A0:A7 4 4 6 PWM Outputs Fault Inputs PWMB Current Sense Inputs 3 Quadrature Decoder 1/ Quad B Timer 4 2 SCI1 or GPIO 2 Dedicated GPIO 14 VPP RSTO VREF • Up to 40 MIPS at 80MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • Hardware DO and REP loops • MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes • 31.5K × 16-bit words (64KB) Program Flash • 512 × 16-bit words (1KB) Program RAM •4K × 16-bit words (8KB) Data Flash •2K × 16-bit words (4KB) Data RAM •2K × 16-bit words (4KB) Boot Flash • Up to 64K × 16-bit words (128KB) each of external Program and Data memory • Two 6-channel PWM Modules • Two 4-channel, 12-bit ADCs • Two Quadrature Decoders • CAN 2.0 B Module • Two Serial Communication Interfaces (SCIs) • Serial Peripheral Interface (SPI) • Up to four General Purpose Quad Timers • JTAG/OnCETM port for debugging • 14 Dedicated and 18 Shared GPIO lines • 144-pin LQFP Package *includes TCS pin which is reserved for factory use and is tied to VSS 56F805 General Description |
Similar Part No. - DSP56F805 |
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Similar Description - DSP56F805 |
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