FS6128-04

A simple formula to obtain the “pulling” capability of a crystal oscillator is:

where:

3.2 Phase-Locked Loop (PLL)

The on-chip PLL is a standard frequency- and phase locked loop architecture. The PLL multiplies the reference oscillator frequency to

the desired output frequency by a ratio of integers. The frequency multiplication is exact with a zero synthesis error (unless otherwise

specified).

4.0 Electrical Specifications

Table 3: Absolute Maximum Ratings

Parameter

Symbol

Min.

Max.

Units

7

V

Input voltage, DC

V

Output voltage, DC

V

-50

50

mA

-50

50

mA

Storage temperature range (non-condensing)

-65

150

°C

Ambient temperature range, under bias

-55

125

°C

Junction temperature

125

°C

Re-flow solder profile

Per IPC/JEDEC J-STD-020B

Input static discharge voltage protection (MLD-STD 883E, Method 3015.7)

2

kv

Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress

rating only and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied.

Exposure to maximum rating conditions for extended conditions may affect device performance, functionality and reliability.

CAUTION: ELECTROSTATIC SENSITIVE DEVICE

Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high energy

electrostatic discharge.

Table 4: Operating Conditions

Parameter

Symbol

Conditions/Descriptions

Min.

Typ.

Max.

Units

Supply voltage

3.3V ± 10%

3.0

3.3

3.6

V

Ambient operating temperature range

0

70

°C

Crystal resonator frequency

Functional mode

12

13.5

18

MHz

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