1.2V

V

Cell Voltage

OUT

CD

LVO

(VCn - VC(n-1),

VC6 – GND)

bq77PL157A4225

SLUSA00 – MARCH 2010

www.ti.com

Figure 6. Timing for Overvoltage Sensing (Without Recovery Option – Permanent Latch)

From Level Shift Input

More than six cells can be monitored with multiple bq77PL157 devices by using the LVO and LVIN pins to

cascade or stack multiple parts. The LVO pin from the upper bq77PL157 is connected to the LVIN pin of the

lower bq77PL157. The OUT pin of the lowest bq77PL157 is used to control the activation element while the OUT

pins of the upper bq77PL157 devices are not used.

pin and the LVO pin are both activated. Once the output is activated, the CD pin continues to charge up to its

The delay time from LVIN to either LVO or OUT is minimized by quickly charging the CD pin and is

approximately 10 times faster than the delay time from an overvoltage fault at the direct cell inputs. When more

than two bq77PL157 devices are stacked, this delay time is additive.

The delay time per device can be calculated as follows:

When the LVIN pin changes from a high to low level, an internal switch clamps the CD pin to GND, discharging

To find the total expected delay time from LVIN to OUT, a variable internal latency of approximately 4 - 12 ms

should be added.

Faults detected via LVIN have the highest priority and will interrupt the timing of all lower priority faults.

8

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