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BQ24725 Datasheet(PDF) 8 Page - Texas Instruments |
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BQ24725 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 39 page  bq24725 SLUS702 – JULY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) 4.5 V ≤ VVCC ≤ 24 V, 0°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ACFET GATE DRIVER (ACDRV) IACFET ACDRV charge pump current limit 40 60 mA VACFET Gate drive voltage on ACFET VACDRV–VCMSRC when VVCC> UVLO 5.5 6.1 6.5 V Minimum load resistance between ACDRV RACDRV_LOAD 500 k Ω and CMSRC RACDRV_OFF ACDRV turn-off resistance I = 30µA 5 6.2 7.4 k Ω ACDRV Turn-Off when Vgs voltage is low VACFET_LOW 5.9 V (Specified by design) PWM HIGH SIDE DRIVER (HIDRV) High side driver (HSD) turn-on resistance VBTST – VPH = 5.5 V, I = 10mA 12 20 Ω RDS(on) High side driver turn-off resistance VBTST – VPH = 5.5 V, I = 10mA 0.65 1.3 Ω Bootstrap refresh comparator threshold VBTST – VPH when low side refresh pulse is requested VBTST_REFRESH 3.85 4.3 4.7 V voltage PWM LOW SIDE DRIVER (LODRV) Low side driver (LSD) turn-on resistance VREGN = 6 V, I = 10 mA 15 25 Ω RDS(on) Low side driver turn-off resistance VREGN = 6 V, I = 10 mA 0.9 1.4 Ω PWM DRIVER TIMING tLOW_HIGH Driver dead time from low side to high side 20 ns tHIGH_LOW Driver dead time from high side to low side 20 ns INTERNAL SOFT START ISTEP Soft start current step 64 mA In CCM mode 10m Ω current sensing resistor tSTEP Soft start current step time 240 ms SMBus TIMING CHARACTERISTICS tR SCLK/SDATA rise time 1 ms tF SCLK/SDATA fall time 300 ns tW(H) SCLK pulse width high 4 50 ms tW(L) SCLK Pulse Width Low 4.7 ms tSU(STA) Setup time for START condition 4.7 ms tH(STA) START condition hold time after which first clock pulse is generated 4 ms tSU(DAT) Data setup time 250 ns tH(DAT) Data hold time 300 ns tSU(STOP) Setup time for STOP condition 4 µs t(BUF) Bus free time between START and STOP condition 4.7 ms FS(CL) Clock Frequency 10 100 kHz HOST COMMUNICATION FAILURE ttimeout SMBus bus release timeout(2) 25 35 ms tBOOT Deglitch for watchdog reset signal 10 ms Watchdog timeout period, ChargeOption() 35 44 53 s bit [14:13] = 01(3) Watchdog timeout period, ChargeOption() tWDI 70 88 105 s bit [14:13] = 10(3) Watchdog timeout period, ChargeOption() 140 175 210 s bit [14:13] = 11(3) (Default) (2) Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms). (3) User can adjust threshold via SMBus ChargeOption() REG0x12. 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :bq24725 |
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