TPS386596L33

SLVSA75 – JULY 2010

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web

site at www.ti.com.

Custom threshold voltages from 0.80V to 4.6V, 4.8V to 6.0V are available through the use of factory EEPROM programming. Minimum

order quantities apply. Contact factory for details and availability.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1) (2)

TPS386596

UNIT

Input voltage range, VCC

–0.3 to 7.0

V

–0.3 to 7.0

V

RESETpin current

5

mA

ESD rating, HBM

2

kV

ESD rating, CDM

500

V

Continuous total power dissipation

See Thermal Information

Table

–40 to 150

°C

–40 to 125

°C

–65 to 150

°C

(1)

Stresses beyond those listed under Absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2)

THERMAL INFORMATION

TPS386596

UNITS

DGK (8 PINS)

Junction-to-ambient thermal resistance

183.8

Junction-to-case (top) thermal resistance

70.7

Junction-to-board thermal resistance

72.8

°C/W

Junction-to-top characterization parameter

4.9

Junction-to-board characterization parameter

68.4

Junction-to-case (bottom) thermal resistance

n/a

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

2

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