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EP2A40 Datasheet(PDF) 6 Page - Altera Corporation |
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EP2A40 Datasheet(HTML) 6 Page - Altera Corporation |
6 / 34 page 1–6 Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet Functional Description Configuration Handbook (Complete Two-Volume Set) © December 2009 Altera Corporation The external flash interface is currently supported in the EPC16 and EPC4 devices. For information about using this feature in the EPC8 device, contact Altera Applica- tions at www.altera.com/support. Enhanced configuration devices have a 3.3-V core and I/O interface. The controller chip is a synchronous system that implements the various interfaces and features. Figure 1–1 shows a block diagram of the enhanced configuration device. The controller chip features three separate interfaces: ■ A configuration interface between the controller and the Altera FPGAs ■ A JTAG interface on the controller that enables ISP of the flash memory ■ An external flash interface that the controller shares with an external processor, or FPGA implementing a Nios® embedded processor (interface available after ISP and configuration) EPC16 Commercial UBGA 88 Intel (1) or Sharp Intel (1) or Sharp Industrial UBGA 88 Intel (1) or Sharp Intel (1) Commercial/ Industrial PQFP 100 Intel (1) or Sharp Intel (1) Note to Table 1–3: (1) For more information, refer to the Process Change Notification PCN0506: Addition of Intel Flash Memory As Source for EPC4, EPC8 and EPC16 Enhanced Configuration Devices. Table 1–3. Enhanced Configuration Devices Flash Memory (Part 2 of 2) Device Grade Package Flash Memory Leaded Lead-Fee Figure 1–1. Enhanced Configuration Device Block Diagram Flash FPGA Controller JTAG/ISP Interface Enhanced Configuration Device Shared Flash Interface Shared Flash Interface |
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