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EPF10K100B Datasheet(PDF) 9 Page - Altera Corporation |
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EPF10K100B Datasheet(HTML) 9 Page - Altera Corporation |
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9 / 34 page  Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet 1–9 Functional Description © December 2009 Altera Corporation Configuration Handbook (Complete Two-Volume Set) Configuration Signals Table 1–4 lists the configuration signal connections between the enhanced configuration device and Altera FPGAs. Fast Passive Parallel Configuration Stratix series and APEX II devices can be configured using the enhanced configuration device in FPP mode. In this mode, the enhanced configuration device sends a byte of data on the DATA[7..0] pins, which connect to the DATA[7..0] input pins of the FPGA, per DCLK cycle. Stratix series and APEX II FPGAs receive byte-wide configuration data per DCLK cycle. Figure 1–2 shows the enhanced configuration device in FPP configuration mode. In this figure, the external flash interface is not used and hence most flash pins are left unconnected (with the few noted exceptions). For specific details about configuration interface connections including pull-up resistor values, supply voltages, and MSEL pin settings, refer to the appropriate FPGA family chapter in the Configuration Handbook. Table 1–4. Configuration Signals Enhanced Configuration Device Pin Altera FPGA Pin Description DATA[] DATA[] Configuration data transmitted from the configuration device to the FPGA, which is latched on the rising edge of DCLK . DCLK DCLK Configuration device generated clock used by the FPGA to latch configuration data provided on the DATA[] pins. nINIT_CONF, which nCONFIG Open-drain output from the configuration device that is used to start FPGA reconfiguration using the initiate configuration (INIT_CONF) JTAG instruction. This connection is not needed if the INIT_CONF JTAG instruction is not needed. If nINIT _CONF is not connected to nCONFIG, nCONFIG must be tied to VCC either directly or through a pull-up resistor. OE nSTATUS Open-drain bidirectional configuration status signal, which is driven low by either device during POR and to signal an error during configuration. Low pulse on OE resets the enhanced configuration device controller. nCS CONF _DONE Configuration done output signal driven by the FPGA. |
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