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SN74LVC2G00 Datasheet(PDF) 1 Page - Texas Instruments

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Part # SN74LVC2G00
Description  DUAL 2-INPUT POSITIVE-NAND GATE
Download  13 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN74LVC2G00 Datasheet(HTML) 1 Page - Texas Instruments

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www.ti.com
FEATURES
Seemechanicaldrawingsfordimensions.
DCTPACKAGE
(TOP VIEW)
DCUPACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOMVIEW)
1
V
CC
8
1A
2
7
1B
1Y
3
6
2Y
2B
4
5
GND
2A
3
6
2B
2Y
8
1
V
CC
1A
5
GND
4
2A
2
7
1Y
1B
GND
5
4
2A
3 6
2B
2Y
2 7
1Y
1B
8
V
CC
1
1A
DESCRIPTION/ORDERING INFORMATION
SN74LVC2G00
DUAL 2-INPUT POSITIVE-NAND GATE
SCES193L – APRIL 1999 – REVISED JANUARY 2007
• Available in the Texas Instruments
• Typical V
OHV (Output VOH Undershoot)
NanoFree™ Package
>2 V at V
CC = 3.3 V, TA = 25°C
• Supports 5-V V
CC Operation
• I
off Supports Partial-Power-Down Mode
Operation
• Inputs Accept Voltages to 5.5 V
• Latch-Up Performance Exceeds 100 mA Per
• Max t
pd of 4.3 ns at 3.3 V
JESD 78, Class II
• Low Power Consumption, 10-µA Max I
CC
• ESD Protection Exceeds JESD 22
• ±24-mA Output Drive at 3.3 V
2000-V Human-Body Model (A114-A)
• Typical V
OLP (Output Ground Bounce)
1000-V Charged-Device Model (C101)
<0.8 V at V
CC = 3.3 V, TA = 25°C
This dual 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G00 performs the Boolean function Y = A
⋅ B or Y = A + B in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
NanoFree™ – WCSP (DSBGA)
Reel of 3000
SN74LVC2G00YZPR
_ _ _CA_
0.23-mm Large Bump – YZP (Pb-free)
SSOP – DCT
Reel of 3000
SN74LVC2G00DCTR
C00_ _ _
–40
°C to 85°C
Reel of 3000
SN74LVC2G00DCUR
VSSOP – DCU
C00_
Reel of 250
SN74LVC2G00DCUT
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2)
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
• = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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