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74LVC2G125DCTRE4 Datasheet(PDF) 1 Page - Texas Instruments |
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74LVC2G125DCTRE4 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 14 page www.ti.com FEATURES Seemechanicaldrawingsfordimensions. DCTPACKAGE (TOP VIEW) DCUPACKAGE (TOP VIEW) YZP PACKAGE (BOTTOMVIEW) 1 V CC 8 1OE 2 7 1A 2OE 3 6 2Y 1Y 4 5 GND 2A 3 6 1Y 2Y 8 1 V CC 1OE 5 GND 4 2A 2 7 2OE 1A GND 5 4 2A 3 6 1Y 2Y 2 7 2OE 1A 8 V CC 1 1OE DESCRIPTION/ORDERING INFORMATION SN74LVC2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES204M – APRIL 1999 – REVISED JANUARY 2007 • Available in the Texas Instruments • I off Supports Partial-Power-Down Mode NanoFree™ Package Operation • Supports 5-V V CC Operation • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • Inputs Accept Voltages to 5.5 V • ESD Protection Exceeds JESD 22 • Max t pd of 4.3 ns at 3.3 V – 2000-V Human-Body Model (A114-A) • Low Power Consumption, 10-µA Max I CC – 200-V Machine Model (A115-A) • ±24-mA Output Drive at 3.3 V – 1000-V Charged-Device Model (C101) • Typical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, TA = 25°C • Typical V OHV (Output VOH Undershoot) >2 V at V CC = 3.3 V, TA = 25°C The SN74LVC2G125 is a dual bus buffer gate, designed for 1.65-V to 5.5-V VCC operation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING(2) NanoFree™ – WCSP (DSBGA) Reel of 3000 SN74LVC2G125YZPR _ _ _CM_ 0.23-mm Large Bump – YZP (Pb-free) SSOP – DCT Reel of 3000 SN74LVC2G125DCTR C25_ _ _ –40°C to 85°C Reel of 3000 SN74LVC2G125DCUR VSSOP – DCU C25_ Reel of 250 SN74LVC2G125DCUT (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. (2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 1999–2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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