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SN74LVTH125DR Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LVTH125DR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 17 page SN54LVTH125, SN74LVTH125 3.3V ABT QUADRUPLE BUS BUFFERS WITH 3STATE OUTPUTS SCBS703I − AUGUST 1997 − REVISED OCTOBER 2003 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. FUNCTION TABLE (each buffer) INPUTS OUTPUT OE A OUTPUT Y L H H L LL H X Z logic diagram (positive logic) 1 1OE 2 1A 1Y 3 4 2OE 5 2A 2Y 6 10 3OE 9 3A 3Y 8 13 4OE 12 4A 4Y 11 Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages. |
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