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NCV8855 Datasheet(PDF) 8 Page - ON Semiconductor |
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NCV8855 Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 24 page NCV8855 http://onsemi.com 8 ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1− = VISNS2+ = VISNS2− = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range −40°C v TJ v 150°C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation. Parameter Unit Max Typ Min Conditions Symbol SWITCH−MODE POWER SUPPLY CONTROLLER (SMPS1, VOUT1) SPECIFICATIONS Error Amplifier Dc gain (Note 1) 70 85 dB Gain−bandwidth product (Note 1) 8 10 MHz SW_FB1 input bias current SW_FB1 = 0.8 V 100 nA Input offset voltage (Note 1) 800 mV Slew rate CCOMP1 = 50 pF, $1 mA dc load Slew rate within ramp voltage levels (Note 1) 6 8 V/ms COMP1 source current VCOMP1 = 2.2 V 1.5 8 mA VCOMP1 = 3.2 V 1.6 8 mA COMP1 sink current VCOMP1 = 2.2 V 1.1 8 mA VCOMP1 = 1.1 V 0.7 8 mA Minimum COMP1 voltage ICOMP1 = 500 mA 1.05 V Maximum COMP1 voltage ICOMP1 = 2 mA 3.3 V Ramp maximum voltage 2.8 3.0 3.2 V Ramp minimum voltage 1.1 1.2 1.3 V Ramp voltage amplitude VRAMP1 1.6 1.8 2.0 V Duty Cycle Limitations Minimum off time tMINOFF1 GH1 falling to GL1 rising 80 140 200 ns Minimum pulse width tMINON1 GH1 rising to GH1 falling 120 250 300 ns Gate Driver GH1 source current VGH1 – VSN1 = 4 V, TJ = 25°C 1.5 A GH1 sink current VGH1 – VSN1 = 2 V, TJ = 25°C 1.5 A GL1 source current VGL1 – PGND = 4 V, TJ = 25°C 1.5 A GL1 sink current VGL1 – PGND = 1 V, TJ = 25°C 1.5 A SN1 falling to GL1 rising, non−overlap time tNOLT 30 70 ns GL1 falling to GH1 rising, non−overlap time 30 70 ns SN1 falling non−overlap threshold voltage 1.0 1.8 3.0 V GL1 falling non−overlap threshold voltage 2 V SN1 falling override timer 50 100 150 ns SWITCH−MODE POWER SUPPLY REGULATOR (SMPS2, VOUT2) SPECIFICATIONS Over Current Protection Internal current limit 2.5 3.05 4.2 A Current limit blanking time 100 200 ns Short circuit threshold voltage SCTH2 VSW_FB2 % of VREF 75 85 95 % Short circuit protection startup delay From SYS_EN rising edge, % of tSS2, SW_FB2 = 0.5 V 100 125 150 % 1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters. |
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