NLSX4014DR2G datasheet(8/13 Pages) ONSEMI

Part #	NLSX4014DR2G

Description	4-Bit 100 Mb/s Configurable Dual-Supply Level Translator

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Manufacturer	ONSEMI [ON Semiconductor]

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NLSX4014

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8

ENABLE / DISABLE TIME MEASUREMENTS

Symbol

Parameter

Test Conditions

(Note 12)

VCC (V)

(Note 13)

VL (V)

(Note 14)

−405C to +855C

Unit

Min

Typ

(Note 15)

Max

tEN−VCC Turn−On Enable Time (Output =

I/O_VCC, tpZH)

CIOVCC = 15 pF

1.3 to 4.5 0.9 to (VCC – 0.4)

130

180

ns

Turn−On Enable Time (Output =

I/O_VCC, tpZL)

CIOVL = 15 pF

1.3 to 4.5 0.9 to (VCC – 0.4)

100

150

ns

tEN−VL

Turn−On Enable Time (Output =

I/O_VL, tpZH)

CIOVCC = 15 pF

1.3 to 4.5 0.9 to (VCC – 0.4)

95

185

ns

Turn−On Enable Time (Output =

I/O_VL, tpZL)

CIOVL = 15 pF

1.3 to 4.5 0.9 to (VCC – 0.4)

70

110

ns

tDIS−VCC Turn−Off Disable Time (Output =

I/O_VCC, tpHZ)

CIOVCC = 15 pF

1.3 to 4.5 0.9 to (VCC – 0.4)

175

250

ns

Propagation Delay (Output =

I/O_VCC, tPLZ)

CIOVL = 15 pF

1.3 to 4.5 0.9 to (VCC – 0.4)

150

190

ns

tDIS−VL Turn−Off Disable Time (Output =

I/O_VL, tpHZ)

CIOVCC = 15 pF

1.3 to 4.5 0.9 to (VCC – 0.4)

180

250

ns

Propagation Delay (Output = I/O_VL,

tPLZ)

CIOVL = 15 pF

1.3 to 4.5 0.9 to (VCC – 0.4)

160

220

ns

12.Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified.

13.VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions.

14.VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However,

during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V.

15.Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25 °C. All units are production tested at TA = +25 °C. Limits over the operating

temperature range are guaranteed by design.

NLSX4014

EN

I/O VL

VL

VCC

CIOVCC

tRISE/FALL v

3 ns

I/O VL

I/O VCC

tPD_VL−VCC

90%

50%

10%

90%

50%

10%

tPD_VL−VCC

tF−VCC

tR−VCC

Figure 5. Driving I/O VL Test Circuit and Timing

I/O VCC

NLSX4014

EN

I/O VL

VL

VCC

CIOVL

Source

tRISE/FALL v 3 ns

I/O VCC

I/O VL

tPD_VCC−VL

90%

50%

10%

90%

50%

10%

tPD_VCC−VL

tF−VL

tR−VL

Figure 6. Driving I/O VCC Test Circuit and Timing

I/O VCC

Source

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