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LM3S9B90-EQN20-C1 Datasheet(PDF) 3 Page - Texas Instruments |
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LM3S9B90-EQN20-C1 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 1185 page Table of Contents Revision History ............................................................................................................................. 36 About This Document .................................................................................................................... 41 Audience .............................................................................................................................................. 41 About This Manual ................................................................................................................................ 41 Related Documents ............................................................................................................................... 41 Documentation Conventions .................................................................................................................. 42 1 Architectural Overview .......................................................................................... 44 1.1 Functional Overview ...................................................................................................... 46 1.1.1 ARM Cortex™-M3 ......................................................................................................... 46 1.1.2 On-Chip Memory ........................................................................................................... 48 1.1.3 External Peripheral Interface ......................................................................................... 49 1.1.4 Serial Communications Peripherals ................................................................................ 50 1.1.5 System Integration ........................................................................................................ 56 1.1.6 Analog .......................................................................................................................... 62 1.1.7 JTAG and ARM Serial Wire Debug ................................................................................ 64 1.1.8 Packaging and Temperature .......................................................................................... 64 1.2 Target Applications ........................................................................................................ 64 1.3 High-Level Block Diagram ............................................................................................. 65 1.4 Additional Features ....................................................................................................... 67 1.4.1 Memory Map ................................................................................................................ 67 1.4.2 Hardware Details .......................................................................................................... 67 2 ARM Cortex-M3 Processor Core ........................................................................... 68 2.1 Block Diagram .............................................................................................................. 69 2.2 Functional Description ................................................................................................... 69 2.2.1 Programming Model ...................................................................................................... 69 2.2.2 Serial Wire and JTAG Debug ......................................................................................... 76 2.2.3 Embedded Trace Macrocell (ETM) ................................................................................. 76 2.2.4 Trace Port Interface Unit (TPIU) ..................................................................................... 76 2.2.5 ROM Table ................................................................................................................... 77 2.2.6 Memory Protection Unit (MPU) ....................................................................................... 77 2.2.7 Nested Vectored Interrupt Controller (NVIC) .................................................................... 77 2.2.8 System Timer (SysTick) ................................................................................................. 78 3 Memory Map ........................................................................................................... 81 4 Interrupts ................................................................................................................. 84 5 JTAG Interface ........................................................................................................ 87 5.1 Block Diagram .............................................................................................................. 88 5.2 Signal Description ......................................................................................................... 88 5.3 Functional Description ................................................................................................... 89 5.3.1 JTAG Interface Pins ...................................................................................................... 89 5.3.2 JTAG TAP Controller ..................................................................................................... 91 5.3.3 Shift Registers .............................................................................................................. 91 5.3.4 Operational Considerations ............................................................................................ 92 5.4 Initialization and Configuration ....................................................................................... 94 5.5 Register Descriptions .................................................................................................... 95 3 June 14, 2010 Texas Instruments-Advance Information Stellaris® LM3S9B90 Microcontroller |
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