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SN65LVPE502RGER Datasheet(PDF) 9 Page - Texas Instruments |
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SN65LVPE502RGER Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 27 page  SN65LVPE502 www.ti.com SLLSE29 – APRIL 2010 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TRANSMITTER AC/DC RL =100Ω +1%, DEx, OSx = NC, Transition 800 1000 1200 Bit RL =100Ω +1%, DEx, OSx = GND VTXDIFF_TB_PP 870 Transition Bit RL =100Ω +1%, DEx, OSx = VCC 1085 Differential peak-to-peak Output Transition Bit Voltage mV RL =100Ω +1%, DEx=NC, (VID = 800, 1200 mVpp, 5Gbps) 665 OSx = 0,1,NC Non-Transition Bit RL =100Ω +1%, DEx=0, VTXDIFF_NTB_PP 510 OSx = 0,1,NC Non-Transition Bit RL =100Ω +1%, DEx=1 375 OSx = 0,1,NC Non-Transition Bit –3.0 –3.5 –4.0 OS1,2 = NC (for OS1,2 = 1 and 0 see De-Emphasis Level –6.0 dB Table 2) –8.5 TDE De-Emphasis Width 0.85 UI Zdiff_TX DC Differential Impedance 72 90 120 Ω ZCM_TX DC Common Mode Impedance Measured w.r.t to AC ground over 0-500mV 18 23 30 Ω f = 50 MHz – 1.25 GHz 9 10 RLdiff_TX Differential Return Loss dB f = 1.25 GHz – 2.5 GHz 6 7 RLCM_TX Common Mode Return Loss f = 50 MHz – 2.5 GHz 11 12 dB ITX_SC TX short circuit current TX± shorted to GND 60 mA VTX_CM_DC Transmitter DC common-mode voltage 2.0 2.6 3.0 V VTX_CM_AC_Active TX AC common mode voltage active 30 100 mVpp Electrical idle differential peak to peak VTX_idle_diff-AC-pp HPF to remove DC 0 10 mV output voltage Absolute delta of DC CM voltage VTX_CM_DeltaU1-U0 35 200 mV during active and idle states DC Electrical idle differential output Voltage must be low pass filtered to remove VTX_idle_diff-DC 0 10 mV voltage any AC component Voltage change to allow receiver Positive voltage to sense receiver Vdetect 600 mV detect termination tR,tF Output Rise/Fall time 30 50 ps 20%-80% of differential voltage measure 1" from the output pin tRF_MM Output Rise/Fall time mismatch 20 ps De-Emphasis = –3.5dB (CH 0 and CH 1). Tdiff_LH, Tdiff_HL Differential Propagation Delay Propagation delay between 50% level at 290 350 ps input and output See Figure 5 tidleEntry tidleExit Idle entry and exit times See Figure 6 4 6 ns CTX Tx input capacitance to GND At 2.5 GHz 1.25 pF EQUALIZATION TTX-EYE (1) (2) Total Jitter (Tj) at point A 0.14 0.5 DJTX (2) Deterministic Jitter (Dj) Device setting: OS1 = L, DE1 = H, EQ1 = L 0.06 0.3 UIpp(3) RJTX (2) (4) Random Jitter (Rj) 0.08 0.2 TTX-EYE (1) (2) Total Jitter (Tj) at point B 0.14 0.5 DJTX (2) Deterministic Jitter (Dj) Device setting: OS2 = H, DE2 = H, EQ2 = L 0.06 0.3 UIpp(3) RJTX (2) (4) Random Jitter (Rj) 0.08 0.2 (1) Includes Rj at 10-12 (2) Measured at the end of reference channel in Figure 8 with K28.5 pattern, VID=1000mVpp, 5Gbps, –3.5dB DE from source. (3) UI = 200ps (4) Rj calculated as 14.069 times the RMS random jitter for 10-12 BER Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): SN65LVPE502 |
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