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MSP430F5435AIPNR Datasheet(PDF) 2 Page - Texas Instruments |
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MSP430F5435AIPNR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 99 page MSP430F543x, MSP430F541x SLAS612C – AUGUST 2009 – REVISED MARCH 2010 www.ti.com DESCRIPTION The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 5 µs. The MSP430F543x and MSP430F541x series are microcontroller configurations with three 16-bit timers, a high performance 12-bit analog-to-digital (A/D) converter, up to four universal serial communication interfaces (USCI), hardware multiplier, DMA, real-time clock module with alarm capabilities, and up to 87 I/O pins. Typical applications for this device include analog and digital sensor systems, digital motor control, remote controls, thermostats, digital timers, hand-held meters, etc. Family members available are summarized in Table 1. Table 1. Family Members USCI Flash SRAM ADC12_A Package Channel A: Channel B: Device Timer_A(1) Timer_B(2) I/O (KB) (KB) (Ch) Type UART/IrDA/ SPI/I2C SPI MSP430F5438 256 16 5, 3 7 4 4 14 ext / 2 int 87 100 PZ MSP430F5437 256 16 5, 3 7 2 2 14 ext / 2 int 67 80 PN MSP430F5436 192 16 5, 3 7 4 4 14 ext / 2 int 87 100 PZ MSP430F5435 192 16 5, 3 7 2 2 14 ext / 2 int 67 80 PN MSP430F5419 128 16 5, 3 7 4 4 14 ext / 2 int 87 100 PZ MSP430F5418 128 16 5, 3 7 2 2 14 ext / 2 int 67 80 PN (1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively. (2) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively. Ordering Information(1) PACKAGED DEVICES(2) TA PLASTIC 100-PIN LQFP PLASTIC 80-PIN LQFP (PZ) (PN) MSP430F5438IPZ MSP430F5437IPN –40°C to 85°C MSP430F5436IPZ MSP430F5435IPN MSP430F5419IPZ MSP430F5418IPN (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 2 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated |
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