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TLV320AIC3254 Datasheet(PDF) 11 Page - Texas Instruments |
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TLV320AIC3254 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 168 page  TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP www.ti.com SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 ELECTRICAL CHARACTERISTICS (continued) At 25 °C, AVdd, DVdd, IOVDD = +1.8V, LDO_in = 3.3V, AVdd LDO disabled, f s (Audio) = 48kHz, Cref = 10 µF on REF PIN, PLL disabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RL=16Ω, Output Stage on AVdd = 1.8V 15 THDN < 1%, Input CM=0.9V, Output CM=0.9V Power Delivered mW RL=16 Ω Output Stage on LDOIN = 3.3V, 64 THDN < 1% Input CM=0.9V, Output CM=1.65V AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT Load = 16 Ω (single-ended), 50pF, Headphone Output on AVdd Supply, Input & Output CM=0.75V; AVdd=1.5V, Device Setup DOSR = 128, MCLK=256* fs, Channel Gain = –2dB, word length=20-bits; Processing Block = PRB_P1, Power Tune = PTM_P4 Full scale output voltage (0dB) 0.375 VRMS SNR Signal-to-noise ratio, A-weighted(1) (2) All zeros fed to DAC input 99 dB DR Dynamic range, A-weighted (1) (2) -60dB 1 kHz input full-scale signal 98 dB THD+N Total Harmonic Distortion plus Noise –1dB full-scale, 1-kHz input signal –83 dB AUDIO DAC – MONO DIFFERENTIAL HEADPHONE OUTPUT Load = 32 Ω (differential), 50pF, Headphone Output on LDOIN Supply Input CM = 0.75V, Output CM=1.5V, AVdd=1.8V, LDOIN=3.0V, DOSR = 128 Device Setup MCLK=256* fs, Channel (headphone driver) Gain = 5dB for full scale output signal, word length=16-bits, Processing Block = PRB_P1, Power Tune = PTM_P3 Full scale output voltage (0dB) 1778 mVRMS SNR Signal-to-noise ratio, A-weighted(1) (2) All zeros fed to DAC input 98 dB DR Dynamic range, A-weighted (1) (2) –60dB 1kHz input full-scale signal 96 dB THD Total Harmonic Distortion –3dB full-scale, 1-kHz input signal –82 dB RL=32Ω, Output Stage on LDOIN = 3.3V, 136 mW THDN < 1%, Input CM=0.9V, Output CM=1.65V Power Delivered RL=32Ω Output Stage on LDOIN = 3.0V, 114 mW THDN < 1% Input CM=0.9V, Output CM=1.5V LOW DROPOUT REGULATOR (AVdd) LDOMode = 1, LDOin > 1.95V 1.67 Output Voltage LDOMode = 0, LDOin > 2.0V 1.72 V LDOMode = 2, LDOin > 2.05V 1.77 Output Voltage Accuracy ±2 % Load Regulation Load current range 0 to 50mA 15 mV Line Regulation Input Supply Range 1.9V to 3.6V 5 mV Decoupling Capacitor 1 µF Bias Current 60 µA LOW DROPOUT REGULATOR (DVdd) LDOMode = 1, LDOin > 1.95V 1.67 V Output Voltage LDOMode = 0, LDOin > 2.0V 1.72 LDOMode = 2, LDOin > 2.05V 1.77 Output Voltage Accuracy ±2 % Load Regulation Load current range 0 to 50mA 15 mV Line Regulation Input Supply Range 1.9V to 3.6V 5 mV Decoupling Capacitor 1 µF Bias Current 60 µA Submit Documentation Feedback Electrical Specifications 11 |
Similar Part No. - TLV320AIC3254_09 |
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Similar Description - TLV320AIC3254_09 |
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