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TMS320DM6467CZUTV Datasheet(PDF) 7 Page - Texas Instruments |
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TMS320DM6467CZUTV Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 357 page  2 Revision History TMS320DM6467 Digital Media System-on-Chip www.ti.com SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009 This data manual revision history highlights the technical changes made to the SPRS403E device-specific data manual to make it an SPRS403F revision. Scope: Applicable updates to the DM646x DMSoC device family, specifically relating to the TMS320DM6467 device (all Silicon Revisions 3.0, 1.1, and 1.0) which is now in the production data (PD) stage of development have been incorporated. • Increased the VPIF operating frequency from 99 MHz to 108 MHz for -729 devices • Updated PCI Terminal Functions pin descriptions including the disabling of the IPUs/IPDs in PCI mode (PCIEN = 1) and the addition of the PCI_RSV[0:5] pin descriptions (pins: A9, E9, B10, D10, A11, and D11) • The DM6467 devices now support 512 MB of DDR2 memory • Updated/Changed pin B10 to "PCI_RSV2/INTRQ/GP[18]/EM_RSV0" SEE ADDITIONS/MODIFICATIONS/DELETIONS Global • Added, where applicable, the support of 108-MHz operating frequency for the Video Port Interface (VPIF) peripheral for -729 devices • Added, where applicable, the PCI_RSV[0:5] pin descriptions [A9, E9, B10, E10, A11, and D11], associated footnotes, and muxing functionality • Added, where applicable, the disabling of the IPUs/IPDs on all PCI pins when in PCI mode (PCIEN = 1); it is recommended that additional external resistors be added on PCI_RSV[0:5] pins. • Updated/Changed, where applicable, the EMU RSV pin function from "RSV" to "EMU_RSV0" • Added, where applicable, DDR2 memory has been updated/changed to support 512 MB vs. 256 MB Section 3.1 Table 3-1, Characteristics of the DM6467 Processor: Device Characteristics • Added to the "Configurable Video Port Interface (VPIF)" both 99 MHz and 108 MHz operating frequency ranges • Updated/Changed, under the PLL Options, the DEV_CLKIN frequency multiplier (PLLC2) (27-MHz reference) descriptions Section 3.6 Section 3.6.1, Pin Map (Bottom View): Pin Assignments • Updated/Changed Figure 3-6, Pin Map [Section E] pin names for A9, A11, B10, E9, E10, and D11 Section 3.7.7 Table 3-11, Peripheral Component Interconnect (PCI) Terminal Functions: Peripheral Component • Added the "Also, in PCI mode (PCIEN = 1), the internal ..." paragraph under Note: Interconnect (PCI) Section 4.3.1.2 Table 4-3, DM6467 Default Module States: Module Clock State • Updated/Changed DEFAULT MODULE STATE description of LPSC #1 and #21 • Updated/Changed LPSC # 16 and 17 to be used in combination for the Video Port • Added associated footnote explanation Section 4.7.3 Section 4.7.3.7, CRGEN Signal Muxing: Pin Multiplexing Details • Updated/changed "The two CRGEN modules shared pin with ..." lead-in sentence [Cleared Documentation Feedback Issue] Section 4.8 Section 4.8.1, Pullup/Pulldown Resistors: Debugging Considerations • Added "For most systems, a 20-k Ω resistor can also be used as an external PU/PD ..." paragraph Section 6 Section 6.1, Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted): Device Operating • Updated/Changed the Supply voltage ranges, I/O, 3.3V from "0 V to 3.8 V" to "–0.3 V to 3.8 V" Conditions • Updated/Changed the Supply voltage ranges, I/O, 1.8V from "0 V to 2.6 V" to "–0.3 V to 2.6 V" • Updated/Changed the Storage temperature range, Tstg, (default) from "–65°C to 150°C" to "–55°C to 150 °C" Section 7.3.4 Table 7-2, DM6467 Clock Domains: DM6467 Power and Clock • Updated/Changed the VPIF FIXED RATIO vs. SYSCLK1 FREQUENCY under VPIF for -594 and -729 Domains • Updated/Changed the VPIF PLL MODE for -594 from "74.25" to "99" MHz • Updated/Changed the VPIF PLL MODE for -729 from "72.9" to "104.14" MHz Submit Documentation Feedback Revision History 7 |
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