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TPS657051YZHR Datasheet(PDF) 4 Page - Texas Instruments |
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TPS657051YZHR Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 24 page  TPS657052 TPS657051 SLVSA08 – FEBRUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted: VIN1=VIN2=VINLDO=3.6 V, L=LQMP21P 2.2µH, COUTDCDCx = 10µF, COUTLDO =2.2µF, TA = –40°C to +85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SWITCH High side MOSFET on-resistance VIN1 = VIN2 = 3.6 V 350 750 m Ω RDS(ON) Low side MOSFET on-resistance VIN1 = VIN2 = 3.6 V 350 600 m Ω ILIMF Forward current limit 3.3V ≤ VIN1 = VIN2 ≤ 6.0 V 550 650 770 mA IOUTDCDC1/2 DCDC1/DCDC2 output current VIN1 = VIN2 > 3.3 V , L = 2.2 µH 400 mA OSCILLATOR fSW Oscillator frequency 2.03 2.25 2.48 MHz OUTPUT VOUT1 DCDC1 default output voltage VIN1 = VIN2 ≥ 3.3 V 3.3 V VOUT2 DCDC2 default output voltage VIN1 = VIN2 ≥ 3.3 V 1.8 V IFB FB pin input current DCDC converter disabled 0.1 µA VIN1 = VIN2 = 3.3 V to 6.0 V, +1% voltage DC output voltage accuracy(1) positioning active; PFM operation, 0 mA < IOUT +1% +3% < IOUTMAX VOUT VIN1 = VIN2 = 3.3 V to 6.0 V, PWM operation, DC output voltage accuracy –1.5% +1.5% 0 mA < IOUT < IOUTMAX DC output voltage load regulation PWM operation 0.5 %/A tStart Start-up time Time from active EN to Start switching 200 µs tRamp VOUT ramp time Time to ramp from 5% to 95% of VOUT 250 µs Internal discharge resistor at L1 or RDIS L2 DCDC1 or DCDC2 disabled 250 400 600 Ω (TPS657051 Only) THERMAL PROTECTION SEPARATELY FOR DCDC1, DCDC2 AND LDO1 TSD Thermal shutdown Increasing junction temperature 150 °C Thermal shudown hysteresis Decreasing junction temperature 30 °C VLDO, LOW DROPOUT REGULATOR VINLDO Input voltage range for LDO 1.7 6.0 V VLDO TPS657051 LDO default output 3.0 V voltage(2) VLDO TPS657052 LDO default output 2.8 V voltage(3) IO Output current for LDO 200 mA ISC LDO short circuit current limit VLDO = GND 340 400 550 mA Dropout voltage at LDO IO = 200 mA 200 mV Output voltage accuracy for LDO IO = 100 mA, VOUT = 2.8V –2% +2% VINLDO = VLDO + 0.5V (min. 1.7 V) to 6 V, Line regulation for LDO –1% 1% IO = 50 mA Load regulation for LDO IO = 1 mA to 200 mA for LDO –1% 1% fNOISE ≤ 10 kHz, COUT ≥ 2.2 µf Vin = 5.0 V, PSRR Power supply rejection ratio 50 dB Vout = 2.8 V, IOUT = 100 mA Vn Ouput noise voltage Vout = 2.8 V, BW = 10Hz to 100kHz 160 µV RMS Internal soft-start when LDO is enabled; Time to tRamp VOUT ramp time 200 µs ramp from 5% to 95% of VOUT RDIS Internal discharge resistor at VLDO LDO disabled 250 400 550 Ω (1) In Power Save Mode (PFM), the internal reference voltage is 1.01 × Vref. (2) VINLDO > 3.0V (3) VINLDO > 2.8V 4 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS657052 TPS657051 |
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