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TPS65072RSLR Datasheet(PDF) 7 Page - Texas Instruments |
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TPS65072RSLR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 93 page TPS65070, TPS65072, TPS65073 TPS650731, TPS650732 www.ti.com SLVS950B – JULY 2009 – REVISED DECEMBER 2009 DCDC3 CONVERTER (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Internal resistor divider, I2C Fixed output voltage range 0.725 3.3 V selectable (Default setting) For DEFDCDC3 = LOW 1.0 Default output voltage for TPS65070 For DEFDCDC3 = HIGH 1.2 For DEFDCDC3 = LOW 1.2 Default output voltage for TPS65072 V Vout For DEFDCDC3 = HIGH 1.4 For DEFDCDC3 = LOW 1.2 Default output voltage for TPS65073, TPS650731, TPS650732 For DEFDCDC3 = HIGH 1.35 DC output voltage accuracy; PFM mode (1) –2% 3% VINDCDC3 = 2.8 V to 6.3 V; 0 mA ≤ IO ≤ 1.5 A DC output voltage accuracy; PWM mode (1) –1.5% 1.5% Vout DC output voltage accuracy with resistor divider at DEFDCDC3; PFM –2% 3% VINDCDC3 = VDCDC3 +0.3 V (min 2.8 V) to 6.3 V; 0 mA ≤ IO ≤ 1.5A Vout DC output voltage accuracy with resistor divider at DEFDCDC3; PWM –1% 1% ΔVOUT Power save mode ripple voltage IOUT = 1 mA, PFM mode (2) 40 mVpp Time from active EN to Start tStart Start-up time 170 μs switching Time to ramp from 5% to 95% of tRamp VOUT ramp up time 250 μs VOUT Vo - power good threshold rising voltage 5% Vo - power good threshold falling voltage 10% RDIS Internal discharge resistor at L3 –35% 250 35% Ω (1) Output voltage specification does not include tolerance of external voltage programming resistors. Output voltage in PFM mode is scaled to +1% of nominal value. (2) Configuration L= 2.2 μH, COUT = 10 μF Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): TPS65070 TPS65072 TPS65073 TPS650731, TPS650732 |
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