Electronic Components Datasheet Search |
|
CDCE706PWRG4 Datasheet(PDF) 8 Page - Texas Instruments |
|
|
CDCE706PWRG4 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 40 page CDCE706 SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008 ........................................................................................................................................... www.ti.com DEVICE CHARACTERISTICS (continued) over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1 PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT LVCMOS PARAMETER FOR VCCOUT = 2.5-V Mode (9) VCCOUT = 2.3 V, IOH = 0.1 mA 2.2 VOH LVCMOS high-level output voltage VCCOUT = 2.3 V, IOH = –3 mA 1.7 V VCCOUT = 2.3 V, IOH = –4 mA 1.5 VCCOUT = 2.3 V, IOL = 0.1 mA 0.1 VOL LVCMOS low-level output voltage VCCOUT = 2.3 V, IOL = 3 mA 0.5 V VCCOUT = 2.3 V, IOL = 4 mA 0.85 All PLL bypass 9 tPLH, Propagation delay ns tPHL VCO bypass 11 tr0/tf0 Rise and fall time for output slew rate 0 VCCOUT = 2.5 V (20%–80%) 2 3.9 5.6 ns tr1/tf1 Rise and fall time for output slew rate 1 VCCOUT = 2.5 V (20%–80%) 1.8 2.9 4.4 ns tr2/tf2 Rise and fall time for output slew rate 2 VCCOUT = 2.5 V (20%–80%) 1.3 2 3.2 ns Rise and fall time for output slew rate 3 tr3/tf3 VCCOUT = 2.5 V (20%–80%) 0.4 0.8 1.1 ns (default configuration) fOUT = 50 MHz 60 105 1 PLL, 1 output fOUT = 245.76 MHz 50 85 tjit(cc) Cycle-to-cycle jitter(10)(11) ps fOUT = 50 MHz 130 160 3 PLLs, 3 outputs fOUT = 245.76 MHz 60 95 fOUT = 50 MHz 65 110 1 PLL, 1 output fOUT = 245.76 MHz 60 90 tjit(per) Peak-to-peak period jitter(10)(11) ps fOUT = 50 MHz 145 180 3 PLLs, 3 outputs fOUT = 245.76 MHz 70 105 tsk(o) Output skew (see(12) and Table 5) 2-ns rise/fall time at fVCO = 150 MHz, Pdiv = 3 250 ps odc Output duty cycle(13) fVCO = 100 MHz, Pdiv = 1 45% 55% SMBus PARAMETER VIK SCLK and SDATA input clamp voltage VCC = 3 V, II = –18 mA –1.2 V ILK SCLK and SDATA input current VI = 0 V or VCC, VCC = 3.6 V ±5 µA VIH SCLK input, high voltage 2.1 V VIL SCLK input, low voltage 0.8 V VOL SDATA low-level output voltage IOL = 4 mA, VCC = 3 V 0.4 V Input capacitance at SCLK VI = 0 V or VCC 3 10 pF CI Input capacitance at SDATA VI = 0 V or VCC 3 10 pF (9) There is a limited drive capability at output supply voltage of 2.5 V. For proper termination, see the CDCx706/x906 Termination and Signal Integrity Guidelines application report, SCAA080. (10) 50,000 cycles (11) Jitter depends on configuration. Jitter data is normal tr/tf, input frequency = 3.84 MHz, fVCO = 245.76 MHz. (12) The tsk(o) specification is only valid for equal loading of all outputs. (13) odc depends on output rise and fall time (tr/tf). The data is for normal tr/tf and is valid for both SSC on and off. 8 Submit Documentation Feedback Copyright © 2005–2008, Texas Instruments Incorporated Product Folder Link(s): CDCE706 |
Similar Part No. - CDCE706PWRG4 |
|
Similar Description - CDCE706PWRG4 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |