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SN74AUP2G125YZPR Datasheet(PDF) 2 Page - Texas Instruments

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Part # SN74AUP2G125YZPR
Description  LOW-POWER DUAL BUS BUFFER GATE WITH 3-STATE OTPUTS
Download  21 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN74AUP2G125YZPR Datasheet(HTML) 2 Page - Texas Instruments

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AUP
LVC
AUP
AUP
LVC
Static-Power Consumption
(
µA)
Dynamic-Power Consumption
(pF)
Single, dual, and triple gates
3.3-V
Logic
3.3-V
Logic
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
0
5
10
15
20
25
30
35
40
45
Time − ns
AUP1G08 data at CL = 15 pF
Output
Input
Switching Characteristics at 25 MHz
SN74AUP2G125
SCES688D – JANUARY 2007 – REVISED MAY 2010
www.ti.com
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
The SN74AUP2G125 is a dual bus buffer gate designed for 0.8-V to 3.6-V VCC operation. This device features
dual line drivers with 3-state outputs. Each output is disabled when the corresponding output-enable (OE) input is
high. This device has the input-disable feature, which allows floating input signals.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION(1)
ORDERABLE
TOP-SIDE
TA
PACKAGE(2)
PART NUMBER
MARKING(3)
NanoStar™ – WCSP (DSBGA)
Reel of 3000
SN74AUP2G125YFPR
_ _ _ HM_
0.23-mm Large Bump – YFP (Pb-free)
NanoStar™ – WCSP (DSBGA)
Reel of 3000
SN74AUP2G125YZPR
_ _ _ HM_
0.23-mm Large Bump – YZP (Pb-free)
–40°C to 85°C
uQFN – DQE
Reel of 5000
SN74AUP2G125DQER
PV
QFN – RSE
Reel of 5000
SN74AUP2G125RSER
PV
VSSOP – DCU
Reel of 3000
SN74AUP2G125DCUR
H25_
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3)
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
DCU: The actual top-side marking has one additional character to designate the wafer fab/assembly site.
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE
A
L
H
H
L
L
L
H
X(1)
Z
(1)
Floating inputs allowed.
2
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Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP2G125


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