Electronic Components Datasheet Search |
|
SN74LVC1G00DBVR Datasheet(PDF) 1 Page - Texas Instruments |
|
|
SN74LVC1G00DBVR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 16 page See mechanical drawings for dimensions. DBV PACKAGE (TOP VIEW) 5 1 V CC A 2 B 3 4 GND Y DRL PACKAGE (TOP VIEW) 2 B V CC 5 1 A 3 4 GND GND Y DCK PACKAGE (TOP VIEW) 2 B 3 4 GND V CC 5 A Y 1 YZP PACKAGE (BOTTOM VIEW) 2 B V CC 1 5 A GND 4 3 Y SN74LVC1G00 www.ti.com SCES212V – APRIL 1999 – REVISED FEBRUARY 2010 SINGLE 2-INPUT POSITIVE-NAND GATE Check for Samples: SN74LVC1G00 1 FEATURES • Available in the Texas Instruments NanoStar™ • Ioff Supports Partial-Power-Down Mode Package Operation • Supports 5-V VCC Operation • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • Inputs Accept Voltages to 5.5 V • ESD Protection Exceeds JESD 22 • Max tpd of 3.8 ns at 3.3 V – 2000-V Human-Body Model (A114-A) • Low Power Consumption, 10-mA Max ICC – 1000-V Charged-Device Model (C101) • ±24-mA Output Drive at 3.3 V DESCRIPTION/ORDERING INFORMATION This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G00 performs the Boolean function Y = A ● B or Y = A + B in positive logic. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION(1) TA PACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING(3) NanoStar™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP SN74LVC1G00YZPR _ _ _ CA_ (Pb-free) Reel of 3000 SN74LVC1G00DBVR SOT (SOT-23) – DBV C00_ –40°C to 85°C Reel of 250 SN74LVC1G00DBVT Reel of 3000 SN74LVC1G00DCKR SOT (SC-70) – DCK Reel of 250 SN74LVC1G00DCKT CA_ SOT (SOT-553) – DRL Reel of 4000 SN74LVC1G00DRLR (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ● = Pb-free). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 1999–2010, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
Similar Part No. - SN74LVC1G00DBVR |
|
Similar Description - SN74LVC1G00DBVR |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |