FUNCTIONAL BLOCK DIAGRAM

PFM/PWM

Control Logic

Current Limit

Logic

_

+

Compensation

Soft

Start

Slope Compensation

PFM/PWM

Mode Select

PFM/PWM

Comparator

Error Amplifier

_

+

Current

Sense

Driver

Shoot-Through

Logic

_

+

Undervoltage

Lockout

Bias Supply

10 Ω

_

+

R2

R1

R1 + R2 ≈ 1 MΩ

Power Good

Sync

+

Oscillator

_

+

Load Comparator

Current Sense

+

Offset

Antiringing

FB

N-Channel

Power MOSFET

P-Channel

Power MOSFET

L

PGND

EN

FB

FC (See Note B)

GND

SYNC

EN

(See

Note A)

TPS62000-HT

A.

The adjustable output voltage version does not use the internal feedback resistor divider. The FB pin is directly

connected to the error amplifier.

B.

Do not connect the FC pin to an external power source

PIN FUNCTIONS

PIN

I/O

DESCRIPTION

NAME

Enable. A logic high enables the converter, logic low forces the device into shutdown mode reducing the supply current

EN

I

to less than 1

µA.

FB

I

An external resistive divider is connected to FB. The internal voltage divider is disabled.

Supply bypass pin. A 0.1

µF coupling capacitor should be connected as close as possible to this pin for good high

FC

frequency input voltage supply filtering.

GND

Ground.

L

I/O

Connect the inductor to this pin. L is the switch pin connected to the drain of the internal power MOSFETS.

PGND

Power ground. Connect all power grounds to PGND.

Input for synchronization to external clock signal. Synchronizes the converter switching frequency to an external clock

signal with CMOS level:

SYNC

I

SYNC = HIGH: Low-noise mode enabled, fixed frequency PWM operation is forced.

SYNC = LOW (GND): Power save mode enabled, PFM/PWM mode enabled.

I

Supply voltage input.

Copyright © 2009, Texas Instruments Incorporated

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Product Folder Link(s): TPS62000-HT