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PACVGA200QR Datasheet(PDF) 3 Page - ON Semiconductor |
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PACVGA200QR Datasheet(HTML) 3 Page - ON Semiconductor |
3 / 10 page PACVGA200 Rev. 2 | Page 3 of 10 | www.onsemi.com Ordering Information PART NUMBERING INFORMATION Lead-free Finish Pins Package Ordering Part Number 1 Part Marking 24 QSOP-24 PACVGA200QR PACVGA200QR Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. PIN DESCRIPTIONS LEAD(s) NAME DESCRIPTION 1 V CC4 Positive voltage supply pin. This is an isolated V CC pin for the SYNC_1, SYNC_2, SD1 and SD2 circuits. 2 V CC1 Positive voltage supply pin. This is an isolated V CC pin for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD circuits. 3-5 VIDEO_1, VIDEO_2, VIDEO_3 RGB Video Protection Channels. These pins tie to the RGB video lines (for example, the Blue signal) between the VGA controller device and the video connector. 6 GNDD Digital Ground reference supply pin. 7 GNDA Ground reference supply pin for TERM_1, TERM_2 and TERM_3 pins. 8-10 TERM_1, TERM_2, TERM_3 RGB Video Termination Channels. These pins tie to the RGB video lines (for example, the Blue signal) providing a 75 Ω termination to GNDA for the given video channel. 11 PWR_UP Sync Signal Output 1. Ties to the video connector side of one of the sync lines (for example the Horizontal Sync signal). 12 V CC2 Positive voltage supply pin. This is an isolated V CC pin for the DDC_IN1 and DDC_IN2 input circuits. Defines the logic one level for the DDC_OUTn outputs. 13 V_BIAS Used to derive V CC3 from VCC4 input. 14 V CC3 Positive voltage supply pin. This is an isolated V CC pin for the DDC_OUT1 and DDC_OUT2 ESD protection circuits. 15 DDC_OUT1 DDC Signal Output 1. Connects to the connector side of one of the DDC signals (for example, the bidirectional DDC_Data serial line). 16 DDC_IN1 DDC Signal Input 1. Connects to the VGA Controller side of one of the DDC signals (for example, the bidirectional DDC_Data serial line). 17 DDC_IN2 DDC Signal Input 2. Connects to the VGA Controller side of one of the DDC signals (for example, the bidirectional DDC_Clk). |
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