MC68HC11KW1 datasheet(9/238 Pages) FREESCALE

Part #	MC68HC11KW1

Description	High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

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MC68HC11KW1

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TABLE OF CONTENTS

Paragraph

Number

Page

Number

TITLE

6.4.2

DDRD — Data direction register for port D......................................................6-5

6.5

Port E.....................................................................................................................6-6

6.5.1

PORTE — Port E data register ........................................................................6-6

6.6

Port F .....................................................................................................................6-7

6.6.1

PORTF — Port F data register.........................................................................6-7

6.6.2

DDRF — Data direction register for port F.......................................................6-7

6.7

Port G ....................................................................................................................6-8

6.7.1

PORTG — Port G data register .......................................................................6-8

6.7.2

DDRG — Data direction register for port G .....................................................6-9

6.7.3

PGAR — Port G assignment register ..............................................................6-9

6.8

Port H.....................................................................................................................6-10

6.8.1

PORTH — Port H data register........................................................................6-10

6.8.2

DDRH — Data direction register for port H......................................................6-10

6.9

Port J .....................................................................................................................6-11

6.9.1

PORTJ — Port J data register .........................................................................6-11

6.9.2

DDRJ — Data direction register for port J .......................................................6-11

6.10

Port K.....................................................................................................................6-12

6.10.1

PORTK — Port K data register ........................................................................6-12

6.10.2

DDRK — Data direction register for port K ......................................................6-12

6.11

Internal pull-up resistors ........................................................................................6-13

6.11.1

PPAR — Port pull-up assignment register .......................................................6-13

6.12

System conﬁguration .............................................................................................6-14

6.12.1

OPT2 — System conﬁguration options register 2 ............................................6-14

6.12.2

CONFIG — System conﬁguration register .......................................................6-15

7

SERIAL COMMUNICATIONS INTERFACE

7.1

Data format ............................................................................................................7-2

7.2

Transmit operation .................................................................................................7-2

7.3

Receive operation..................................................................................................7-2

7.4

Wake-up feature ....................................................................................................7-4

7.4.1

Idle-line wake-up ..............................................................................................7-4

7.4.2

Address-mark wake-up ....................................................................................7-4

7.5

SCI error detection ................................................................................................7-5

7.6

SCI registers ..........................................................................................................7-5

7.6.1

SCBDH, SCBDL — SCI baud rate control registers ........................................7-6

7.6.2

SCCR1 — SCI control register 1 .....................................................................7-7

7.6.3

SCCR2 — SCI control register 2 .....................................................................7-9

7.6.4

SCSR1 — SCI status register 1.......................................................................7-10

7.6.5

SCSR2 — SCI status register 2.......................................................................7-11

7.6.6

SCDRH, SCDRL — SCI data high/low registers .............................................7-12

7.7

Status ﬂags and interrupts.....................................................................................7-12

7.7.1

Receiver ﬂags ..................................................................................................7-13

7

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