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TPS63001DRCR Datasheet(PDF) 4 Page - Texas Instruments |
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TPS63001DRCR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 24 page PIN ASSIGNMENTS PGND L1 VIN EN GND L2 PS/SYNC VINA VOUT FB DRCPACKAGE (TOP VIEW) TPS63000 TPS63001 TPS63002 SLVS520B – MARCH 2006 – REVISED JULY 2008........................................................................................................................................................... www.ti.com Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. EN 6 I Enable input. (1 enabled, 0 disabled) FB 10 I Voltage feedback of adjustable versions, must be connected to VOUT on fixed output voltage versions GND 9 Control / logic ground PS/SYNC 7 I Enable / disable power save mode (1 disabled, 0 enabled, clock signal for synchronization) L1 4 I Connection for Inductor L2 2 I Connection for Inductor PGND 3 Power ground VIN 5 I Supply voltage for power stage VOUT 1 O Buck-boost converter output VINA 8 I Supply voltage for control stage PowerPAD™ Must be soldered to achieve appropriate power dissipation. Should be connected to PGND. 4 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): TPS63000 TPS63001 TPS63002 |
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