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74AVC8T245PW Datasheet(PDF) 3 Page - NXP Semiconductors |
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74AVC8T245PW Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 23 page 74AVC8T245_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 28 April 2009 3 of 23 NXP Semiconductors 74AVC8T245 8-bit dual supply translating transceiver; 3-state 5. Pinning information 5.1 Pinning Fig 2. Logic diagram (one channel) 001aai473 to other seven channels DIR A1 VCC(A) VCC(B) OE B1 (1) The die substrate is attached to this pad using conductive die attach material. It cannot be used as a supply pin or input. Fig 3. Pin configuration TSSOP24 Fig 4. Pin configuration DHVQFN24 74AVC8T245 VCC(A) VCC(B) DIR VCC(B) A1 OE A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 A8 B7 GND B8 GND GND 001aai489 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 001aai490 74AVC8T245 Transparent top view B8 A8 GND B7 A7 B6 A6 B5 A5 B4 A4 B3 A3 B2 A2 B1 A1 OE DIR VCC(B) 11 14 10 15 9 16 8 17 7 18 6 19 5 20 4 21 3 22 2 23 terminal 1 index area GND(1) |
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