SSTUA32864_2

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 02 — 9 March 2007

6 of 20

NXP Semiconductors

SSTUA32864

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

6.2 Pin description

[1]

Depends on configuration. See Figure 3, Figure 4, and Figure 5 for ball number.

[2]

Configurations:

Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.

Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.

Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.

[3]

Configurations:

Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.

Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.

Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.

Table 2.

Pin description

Symbol

Pin

Type

Description

GND

B3, B4, D3, D4, F3, F4,

H3, H4, K3, K4, M3,

M4, P3, P4

ground input

ground

A4, C3, C4, E3, E4,

G3, G4, J3, J4, L3, L4,

N3, N4, R3, R4, T4

1.8 V nominal

power supply voltage

VREF

A3, T3

0.9 V nominal

input reference voltage

ZOH

J5

input

reserved for future use

ZOL

J6

input

reserved for future use

CK

H1

differential input positive master clock input

CK

J1

differential input negative master clock input

C0, C1

G6, G5

LVCMOS inputs configuration control inputs

RESET

G2

LVCMOS input

Asynchronous reset input (active LOW). Resets registers and

disables VREF data and clock differential-input receivers.

CSR, DCS

J2, H2

SSTL_18 input

Chip select inputs (active LOW). Disables data outputs

switching when both inputs are HIGH.[2]

D1 to D25

[1]

SSTL_18 input

Data inputs. Clocked in on the crossing of the rising edge of

CK and the falling edge of CK.

DODT

[1]

SSTL_18 input

The outputs of this register will not be suspended by DCS and

CSR control.

DCKE

[1]

SSTL_18 input

The outputs of this register will not be suspended by DCS and

CSR control.

Q1 to Q25,

Q1A to Q14A,

Q1B to Q14B

[1]

1.8 V CMOS

The outputs that are suspended by DCS and CSR control[3].

QCS, QCSA,

QCSB

[1]

1.8 V CMOS

Data outputs that will not be suspended by DCS and CSR

control.

QODT, QODTA,

QODTB

[1]

1.8 V CMOS

Data outputs that will not be suspended by DCS and CSR

control.

QCKE, QCKEA,

QCKEB

[1]

1.8 V CMOS

Data outputs that will not be suspended by DCS and CSR

control.

n.c.

A2, D2, G1

-

Not connected. Ball present but no internal connection to the

die.

DNU

[1]

-

Do-not-use. Ball internally connected to the die which should

be left open-circuit.