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SSTUG32865 Datasheet(PDF) 6 Page - NXP Semiconductors |
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SSTUG32865 Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 28 page SSTUG32865_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 16 August 2007 6 of 28 NXP Semiconductors SSTUG32865 1.8 V DDR2-1G registered buffer with parity 6.2 Pin description Table 3. Pin description Symbol Pin Type Description Ungated inputs DCKE0, DCKE1 U1, U2 SSTL_18 DRAM function pins not associated with Chip Select. DODT0, DODT1 T2, T1 Chip Select gated inputs D0 to D21 M1, B1, B2, C1, C2, D2, D1, E1, E2, F2, M2, F1, G2, R1, L2, H2, N2, N1, G1, P1, R2, P2 SSTL_18 DRAM inputs, re-driven only when Chip Select is LOW. Chip Select inputs DCS0, DCS1, DCS2, DCS3[1] J2, K2, H4, K4 SSTL_18 DRAM Chip Select signals. These pins initiate DRAM address/command decodes, and as such at least one will be LOW when a valid address/command is present. The register can be programmed to re-drive all D-inputs only (CSGATEEN = HIGH) when at least one Chip Select input is LOW. DCS2 and DCS3 are not re-driven and can be left open-circuit to default HIGH by means of its internal pull-up resistors. Re-driven outputs Q0A to Q21A V11, F12, G12, V6, V9, H12, L12, V8, V12, N12, M12, P12, V7, V10, T12, R12, E12, A12, A10, A9, D12, A8 SSTL_18 Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock. Q0B to Q21B U11, F11, G11, U6, U9, H11, L11, U8, U12, N11, M11, P11, U7, U10, T11, R11, E11, A11, B10, B9, D11, B8 QCS0A, QDS1A, QCS0B, QCS1B J12, K12, J11, K11 QCKE0A, QCKE1A, QCKE0B, QCKE1B A7, A6, B7, B6 QODT0A, QODT1A, QODT0B, QODT1B B12, C12, B11, C11 Parity input PARIN A3 SSTL_18 Parity input for the D0 to D21 inputs. Arrives one clock cycle after the corresponding data input. Parity error PTYERR U4 open-drain When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs. PTYERR will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with final parity out timing on the industry-standard DDR2 register with parity (in JEDEC definition). |
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