9397 750 14136

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet

Rev. 01 — 11 March 2005

10 of 28

Philips Semiconductors

SSTUH32865

1.8 V high output drive DDR registered buffer with parity

7.3 Functional differences to SSTU32864

The SSTUH32865 for its basic register functionality, signal definition and performance is

based upon the industry-standard SSTU32864, but provides key operational features

which differ (at least in part) from the industry-standard register in the following aspects:

7.3.1 Chip Select (CS) gating of key inputs (DCS0, DCS1, CSGATEEN)

As a means to reduce device power, the internal latches will only be updated when one or

both of the CS inputs are active (LOW) and CSGATEEN HIGH at the rising edge of the

clock. The 22 ‘Chip-Select-gated’ input signals associated with this function include

addresses (ADDR0 to ADDR15, BA0 to BA2), and RAS, CAS, WE, with the remaining

signals (CS, CKE, ODT) continuously re-driven at the rising edge of every clock as they

are independent of CS. The CS gating function can be disabled by tying CSGATEEN

LOW, enabling all internal latches to be updated on every rising edge of the clock.

7.3.2 Parity error checking and reporting

The SSTUH32865 incorporates a parity function, whereby the signal received on input pin

PARIN is received as parity to the register, one clock cycle later than the CS-gated inputs.

The received parity bit is then compared to the parity calculated across these same inputs

by the register parity logic to verify that the information has not been corrupted. The 22

CS-gated input signals will be latched and re-driven on the first clock, and any error will be

reported one clock cycle later via the PTYERR output pin (driven LOW for two consecutive

clock cycles). PTYERR is an open-drain output, allowing multiple modules to share a

common signal pin for reporting the occurrence of a parity error during a valid command

cycle (coincident with the re-driven signals). This output is driven LOW for two consecutive

clock cycles to allow the memory controller sufficient time to sense and capture the error

even. A LOW state on PTYERR indicates that a parity error has occurred.

7.3.3 Reset (RESET)

Similar to the RESET pin on the industry-standard SSTU32864, this pin is used to clear all

internal latches and all outputs will be driven LOW quickly except the PTYERR output,

which will be floated (and will normally default HIGH by their external pull-up).

7.3.4 Power-up sequence

The reset function for the SSTUH32865 is similar to that of the SSTU32864 except that

the PTYERR signal is also cleared and will be held clear (HIGH) for three consecutive

clock cycles.

Table 5:

Chip Select gating mode

Mode

Signal name

Description

Gating

CSGATEEN

HIGH

Registers only re-drive signals to the DRAMs when

Chip Select inputs are LOW.

Non-gating

CSGATEEN

LOW

Registers always re-drive signals on every clock cycle,

independent of the state of the Chip Select inputs.