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SSTUM32868 Datasheet(PDF) 11 Page - NXP Semiconductors |
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SSTUM32868 Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 30 page SSTUM32868_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 2 March 2007 11 of 30 NXP Semiconductors SSTUM32868 1.8 V DDR2-800 configurable registered buffer with parity [1] Q0 is the previous state of the associated output. [2] DCS2 and DCS3 operate identically to DCS0 and DCS1, except they do not have corresponding re-driven (QCS) outputs. [1] DCS2 and DCS3 operate identically to DCS0 and DCS1 with regard to the parity function. [2] PAR_IN arrives one clock cycle after the data to which it applies. [3] This transition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. [4] QERR0 is the previous state of output QERR. [5] If DCS0, DCS1, DCS2, DCS3 and CSGEN are driven HIGH, the device is placed in Low-Power Mode (LPM). If a parity error occurs on the clock cycle before the device enters the LPM and the QERR output is driven LOW, it stays latched LOW for the LPM duration plus two clock cycles or until RESET is driven LOW. 7.2 Functional information The SSTUM32868 is a 28-bit 1 : 2 configurable registered buffer designed for 1.7 V to 1.9 V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output. HH H H ↑↓ HQ0 HH H H H H H L or H L or H X Q0 Q0 Q0 Q0 L X or floating X or floating X or floating X or floating X or floating X or floating L L L L Table 4. Function table (each flip-flop) …continued Inputs Outputs[1] RESET DCS0[2] DCS1[2] CSGEN CK CK Dn, DODTn, DCKEn Qn QCS0x QCS1x QODTn, QCKEn Table 5. Parity and standby function table Inputs Output RESET DCS0[1] DCS1[1] CK CK ∑ of inputs = H (D1 to D28) PAR_IN[2] QERR[3][4] HL X ↑↓ even L H HL X ↑↓ odd L L HL X ↑↓ even H L HL X ↑↓ odd H H HX L ↑↓ even L H HX L ↑↓ odd L L HX L ↑↓ even H L HX L ↑↓ odd H H HH H ↑↓ XX QERR0[5] H X X L or H L or H X X QERR0 L X or floating X or floating X or floating X or floating X X or floating H |
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