BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F /

Memory Ics

BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV

(10) Random read

BR24C08 / F / FJ / FV

S

T

O

P

A

C

K

R

E

A

D

DATA(n)

SLAVE

ADDRESS

SLAVE

ADDRESS

WORD

ADDRESS(n)

SDA

LINE

S

T

A

R

T

S

T

A

R

T

11

0

0 A2 P1 P0

R

/

W

R

/

W

A

C

K

A

C

K

A

C

K

W

R

I

T

E

11

0

0 A2 P1P0

D7

D0

Fig.13

WA

7

WA

0

BR24C16 / F / FJ / FV

S

T

O

P

A

C

K

R

E

A

D

DATA(n)

SLAVE

ADDRESS

SLAVE

ADDRESS

WORD

ADDRESS(n)

SDA

LINE

S

T

A

R

T

S

T

A

R

T

11

0

0 P2 P1 P0

R

/

W

R

/

W

A

C

K

A

C

K

A

C

K

W

R

I

T

E

11

0

0 P2 P1P0

D7

D0

Fig.14

WA

7

WA

0

BR24E16 / F / FJ / FV

SLAVE

ADDRESS

SDA

LINE

S

T

A

R

T

11

0

0 A2 A1 A0

R

/

W

W

R

I

T

E

Fig.15

S

T

O

P

A

C

K

R

E

A

D

DATA(n)

SLAVE

ADDRESS

S

T

A

R

T

R

/

W

A

C

K

A

C

K

11

0

0 A2 A1A0

D7

D0

WA

0

1st WORD

ADDRESS(n)

2nd WORD

ADDRESS(n)

A

C

K

WA

10

∗

∗

∗

∗

∗

A

C

K

$ This command can read the designated word address data.

$ When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (

µ-COM), the next

word address data can be read.

[All words all read enabled]

(See Fig.16 to 18 for the sequential read cycles.)

$ This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop

condition) by raising SCL to HIGH.